i2c_altera_v.sdo

从MIC输入一段音频然后

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.


// 
// Device: Altera EP2C20F484C8 Package FBGA484
// 

// 
// This SDF file should be used for ModelSim (Verilog HDL output from Quartus II) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "I2C_ALTERA")
  (DATE "12/05/2006 17:29:29")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.datain_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (128:128:128) (128:128:128))
        (PORT d[1] (128:128:128) (128:128:128))
        (PORT d[2] (128:128:128) (128:128:128))
        (PORT d[3] (128:128:128) (128:128:128))
        (PORT d[4] (128:128:128) (128:128:128))
        (PORT d[5] (128:128:128) (128:128:128))
        (PORT d[6] (128:128:128) (128:128:128))
        (PORT d[7] (128:128:128) (128:128:128))
        (PORT d[8] (128:128:128) (128:128:128))
        (PORT d[9] (128:128:128) (128:128:128))
        (PORT d[10] (128:128:128) (128:128:128))
        (PORT d[11] (128:128:128) (128:128:128))
        (PORT d[12] (128:128:128) (128:128:128))
        (PORT d[13] (128:128:128) (128:128:128))
        (PORT d[14] (128:128:128) (128:128:128))
        (PORT d[15] (128:128:128) (128:128:128))
        (PORT clk (1835:1835:1835) (1830:1830:1830))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (167:167:167))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.addr_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1167:1167:1167) (1789:1789:1789))
        (PORT d[1] (921:921:921) (1430:1430:1430))
        (PORT d[2] (1162:1162:1162) (1786:1786:1786))
        (PORT d[3] (1279:1279:1279) (1877:1877:1877))
        (PORT d[4] (1767:1767:1767) (2584:2584:2584))
        (PORT clk (1836:1836:1836) (1831:1831:1831))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (167:167:167))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.we_a_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (384:384:384) (384:384:384))
        (PORT clk (1836:1836:1836) (1831:1831:1831))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (167:167:167))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.active_port_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (1836:1836:1836) (1836:1836:1836))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.wpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2096:2096:2096) (2091:2091:2091))
        (IOPATH (posedge clk) pulse (0:0:0) (2161:2161:2161))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.rpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2096:2096:2096) (2091:2091:2091))
        (IOPATH (posedge clk) pulse (0:0:0) (2546:2546:2546))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.ftpgen_a)
    (DELAY
      (ABSOLUTE
        (PORT clk (2096:2096:2096) (2091:2091:2091))
        (IOPATH (posedge clk) pulse (0:0:0) (3641:3641:3641))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.dataout_a_register)
    (DELAY
      (ABSOLUTE
        (PORT clk (1816:1816:1816) (1811:1811:1811))
        (IOPATH (posedge clk) q (369:369:369) (369:369:369))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (167:167:167))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.datain_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (687:687:687) (1083:1083:1083))
        (PORT d[1] (676:676:676) (1076:1076:1076))
        (PORT d[2] (686:686:686) (1082:1082:1082))
        (PORT d[3] (702:702:702) (1092:1092:1092))
        (PORT d[4] (682:682:682) (1081:1081:1081))
        (PORT d[5] (678:678:678) (1077:1077:1077))
        (PORT d[6] (687:687:687) (1083:1083:1083))
        (PORT d[7] (672:672:672) (1070:1070:1070))
        (PORT d[8] (672:672:672) (1070:1070:1070))
        (PORT d[9] (669:669:669) (1068:1068:1068))
        (PORT d[10] (1026:1026:1026) (1514:1514:1514))
        (PORT d[11] (1027:1027:1027) (1516:1516:1516))
        (PORT d[12] (1021:1021:1021) (1510:1510:1510))
        (PORT d[13] (1008:1008:1008) (1500:1500:1500))
        (PORT d[14] (965:965:965) (1469:1469:1469))
        (PORT d[15] (993:993:993) (1490:1490:1490))
        (PORT clk (1869:1869:1869) (1868:1868:1868))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (167:167:167))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.addr_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1444:1444:1444) (1995:1995:1995))
        (PORT d[1] (1340:1340:1340) (1928:1928:1928))
        (PORT d[2] (1444:1444:1444) (1997:1997:1997))
        (PORT d[3] (1023:1023:1023) (1525:1525:1525))
        (PORT d[4] (1353:1353:1353) (1938:1938:1938))
        (PORT clk (1889:1889:1889) (1888:1888:1888))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (167:167:167))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.rewe_b_register)
    (DELAY
      (ABSOLUTE
        (PORT d[0] (1007:1007:1007) (1358:1358:1358))
        (PORT clk (1889:1889:1889) (1888:1888:1888))
      )
    )
    (TIMINGCHECK
      (SETUP d (posedge clk) (46:46:46))
      (HOLD d (posedge clk) (167:167:167))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_register")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.active_port_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (1889:1889:1889) (1888:1888:1888))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.wpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (2149:2149:2149) (2148:2148:2148))
        (IOPATH (posedge clk) pulse (0:0:0) (2118:2118:2118))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.ftpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (2149:2149:2149) (2149:2149:2149))
        (IOPATH (posedge clk) pulse (0:0:0) (2620:2620:2620))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_ram_pulse_generator")
    (INSTANCE inst2\|altsyncram_component\|auto_generated\|altsyncram1\|ram_block3a0.rpgen_b)
    (DELAY
      (ABSOLUTE
        (PORT clk (2149:2149:2149) (2148:2148:2148))
        (IOPATH (posedge clk) pulse (0:0:0) (3758:3758:3758))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE inst8\|cnt\[15\]\~I)
    (DELAY
      (ABSOLUTE
        (PORT clk (1763:1763:1763) (1755:1755:1755))
        (PORT datain (110:110:110) (110:110:110))
        (IOPATH (posedge clk) regout (310:310:310) (310:310:310))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (211:211:211))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE inst\|Select\~1080_I)
    (DELAY
      (ABSOLUTE
        (PORT datac (475:475:475) (685:685:685))
        (PORT datad (357:357:357) (453:453:453))
        (IOPATH datac combout (378:378:378) (378:378:378))
        (IOPATH datad combout (210:210:210) (210:210:210))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE inst\|Select\~1083_I)
    (DELAY
      (ABSOLUTE
        (PORT datac (338:338:338) (429:429:429))
        (PORT datad (357:357:357) (453:453:453))
        (IOPATH datac combout (378:378:378) (378:378:378))
        (IOPATH datad combout (210:210:210) (210:210:210))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE inst1\|divider\[6\]\~I)
    (DELAY
      (ABSOLUTE
        (PORT clk (1732:1732:1732) (1724:1724:1724))
        (PORT sdata (1644:1644:1644) (2033:2033:2033))
        (PORT aclr (1752:1752:1752) (1749:1749:1749))
        (PORT sload (838:838:838) (838:838:838))
        (PORT ena (1922:1922:1922) (2111:2111:2111))
        (IOPATH (posedge clk) regout (310:310:310) (310:310:310))
        (IOPATH (posedge aclr) regout (273:273:273) (273:273:273))
      )
    )
    (TIMINGCHECK
      (HOLD sdata (posedge clk) (211:211:211))
      (HOLD ena (posedge clk) (211:211:211))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")
    (INSTANCE inst1\|clgen\|reduce_or\~115_I)
    (DELAY
      (ABSOLUTE
        (PORT dataa (851:851:851) (1181:1181:1181))
        (PORT datab (354:354:354) (453:453:453))
        (PORT datad (332:332:332) (429:429:429))
        (IOPATH dataa combout (664:664:664) (664:664:664))
        (IOPATH datab combout (636:636:636) (636:636:636))
        (IOPATH datac combout (401:401:401) (401:401:401))
        (IOPATH datad combout (210:210:210) (210:210:210))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE inst1\|clgen\|cnt\[5\]\~I)
    (DELAY
      (ABSOLUTE
        (PORT clk (1749:1749:1749) (1740:1740:1740))
        (PORT datain (110:110:110) (110:110:110))
        (PORT sdata (1471:1471:1471) (1699:1699:1699))
        (PORT aclr (1756:1756:1756) (1751:1751:1751))
        (PORT sload (1289:1289:1289) (1395:1395:1395))
        (IOPATH (posedge clk) regout (310:310:310) (310:310:310))
        (IOPATH (posedge aclr) regout (273:273:273) (273:273:273))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (211:211:211))
      (HOLD sload (posedge clk) (211:211:211))
      (HOLD sdata (posedge clk) (211:211:211))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE inst1\|clgen\|cnt\[6\]\~I)
    (DELAY
      (ABSOLUTE
        (PORT clk (1749:1749:1749) (1740:1740:1740))
        (PORT datain (110:110:110) (110:110:110))
        (PORT sdata (1712:1712:1712) (2054:2054:2054))
        (PORT aclr (1756:1756:1756) (1751:1751:1751))
        (PORT sload (1289:1289:1289) (1395:1395:1395))
        (IOPATH (posedge clk) regout (310:310:310) (310:310:310))
        (IOPATH (posedge aclr) regout (273:273:273) (273:273:273))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (211:211:211))
      (HOLD sload (posedge clk) (211:211:211))
      (HOLD sdata (posedge clk) (211:211:211))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_ff")
    (INSTANCE inst1\|clgen\|cnt\[8\]\~I)
    (DELAY
      (ABSOLUTE
        (PORT clk (1749:1749:1749) (1740:1740:1740))
        (PORT datain (110:110:110) (110:110:110))
        (PORT sdata (963:963:963) (1164:1164:1164))
        (PORT aclr (1756:1756:1756) (1751:1751:1751))
        (PORT sload (1289:1289:1289) (1395:1395:1395))
        (IOPATH (posedge clk) regout (310:310:310) (310:310:310))
        (IOPATH (posedge aclr) regout (273:273:273) (273:273:273))
      )
    )
    (TIMINGCHECK
      (HOLD datain (posedge clk) (211:211:211))
      (HOLD sload (posedge clk) (211:211:211))
      (HOLD sdata (posedge clk) (211:211:211))
    )
  )
  (CELL
    (CELLTYPE "cycloneii_lcell_comb")