i2c_altera_modelsim.xrf

从MIC输入一段音频然后

instance = comp, \sld_hub_inst|GEN_SHADOW_IRF~0_I , sld_hub_inst|GEN_SHADOW_IRF~0, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[2]~I , sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[2], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRF_D[1][2]~41_I , sld_hub_inst|IRF_D[1][2]~41, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRF_ENA_0|Q[0]~3_I , sld_hub_inst|IRF_ENA_0|Q[0]~3, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRF_ENA_0|Q[0]~I , sld_hub_inst|IRF_ENA_0|Q[0], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRF_ENABLE[1]~76_I , sld_hub_inst|IRF_ENABLE[1]~76, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRF_ENABLE[1]~77_I , sld_hub_inst|IRF_ENABLE[1]~77, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_IRF:1:IRF|Q[2]~I , sld_hub_inst|\GEN_IRF:1:IRF|Q[2], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[1]~feeder_I , sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[1]~feeder, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[1]~I , sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[1], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRF_D[1][1]~40_I , sld_hub_inst|IRF_D[1][1]~40, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_IRF:1:IRF|Q[1]~I , sld_hub_inst|\GEN_IRF:1:IRF|Q[1], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|process1~3_I , inst2|altsyncram_component|auto_generated|mgl_prim2|process1~3, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[0]~96_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[0]~96, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[1]~98_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[1]~98, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[3]~I , sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[3], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRF_D[1][3]~43_I , sld_hub_inst|IRF_D[1][3]~43, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_IRF:1:IRF|Q[3]~I , sld_hub_inst|\GEN_IRF:1:IRF|Q[3], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_IRF:1:IRF|Q[3]~clkctrl_I , sld_hub_inst|\GEN_IRF:1:IRF|Q[3]~clkctrl, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|reduce_nor~1_I , inst2|altsyncram_component|auto_generated|mgl_prim2|reduce_nor~1, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[1]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[1], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2]~100_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2]~100, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[3], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[0]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[0], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_shift_cntr_reg[2], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr~39_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr~39, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr~0_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr~0, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_incr_addr, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0]~75_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0]~75, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[1]~77_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[1]~77, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[2]~79_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[2]~79, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[3]~81_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[3]~81, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[4]~83_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[4]~83, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[4]~I , sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[4], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRF_D[1][4]~44_I , sld_hub_inst|IRF_D[1][4]~44, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_IRF:1:IRF|Q[4]~I , sld_hub_inst|\GEN_IRF:1:IRF|Q[4], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|is_in_use_reg~6_I , inst2|altsyncram_component|auto_generated|mgl_prim2|is_in_use_reg~6, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|is_in_use_reg~I , inst2|altsyncram_component|auto_generated|mgl_prim2|is_in_use_reg, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRSR_D[0]~47_I , sld_hub_inst|IRSR_D[0]~47, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRSR|Q[0]~I , sld_hub_inst|IRSR|Q[0], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[0]~feeder_I , sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[0]~feeder, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[0]~I , sld_hub_inst|\GEN_SHADOW_IRF:1:S_IRF|Q[0], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRF_D[1][0]~42_I , sld_hub_inst|IRF_D[1][0]~42, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_IRF:1:IRF|Q[0]~I , sld_hub_inst|\GEN_IRF:1:IRF|Q[0], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|\GEN_IRF:1:IRF|Q[0]~clkctrl_I , sld_hub_inst|\GEN_IRF:1:IRF|Q[0]~clkctrl, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|process0~11_I , inst2|altsyncram_component|auto_generated|mgl_prim2|process0~11, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[4]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[4], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[3]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[3], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[2]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[2], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[1]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[1], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_addr_reg[0], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[0]~feeder_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[0]~feeder, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|process4~12_I , inst2|altsyncram_component|auto_generated|mgl_prim2|process4~12, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[0]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[0], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRSR_D[1]~48_I , sld_hub_inst|IRSR_D[1]~48, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRSR|Q[1]~I , sld_hub_inst|IRSR|Q[1], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|instruction_decoder|auto_generated|w_anode78w[3]~I , sld_hub_inst|instruction_decoder|auto_generated|w_anode78w[3], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[7]~I , sld_hub_inst|instruction_decoder|auto_generated|dffe1a[7], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|comb~6_I , sld_hub_inst|comb~6, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|RESET|Q[0]~I , sld_hub_inst|RESET|Q[0], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|CLEAR_SIGNAL~0_I , sld_hub_inst|CLEAR_SIGNAL~0, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|CLEAR_SIGNAL~0clkctrl_I , sld_hub_inst|CLEAR_SIGNAL~0clkctrl, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|jtag_state_machine|state~10_I , sld_hub_inst|jtag_state_machine|state~10, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|jtag_state_machine|state[3]~I , sld_hub_inst|jtag_state_machine|state[3], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRSR_ENA~I , sld_hub_inst|IRSR_ENA, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRSR|Q[5]~I , sld_hub_inst|IRSR|Q[5], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[3]~feeder_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[3]~feeder, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[3]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ir_loaded_address_reg[3], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRSR_D[4]~51_I , sld_hub_inst|IRSR_D[4]~51, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRSR|Q[4]~I , sld_hub_inst|IRSR|Q[4], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRSR_D[3]~49_I , sld_hub_inst|IRSR_D[3]~49, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|IRSR|Q[3]~I , sld_hub_inst|IRSR|Q[3], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|instruction_decoder|auto_generated|w_anode1w[3]~I , sld_hub_inst|instruction_decoder|auto_generated|w_anode1w[3], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|instruction_decoder|auto_generated|dffe1a[0]~I , sld_hub_inst|instruction_decoder|auto_generated|dffe1a[0], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|HUB_BYPASS_REG~I , sld_hub_inst|HUB_BYPASS_REG, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|hub_tdo~607_I , sld_hub_inst|hub_tdo~607, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|hub_tdo~610_I , sld_hub_inst|hub_tdo~610, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|jtag_state_machine|state~13_I , sld_hub_inst|jtag_state_machine|state~13, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|hub_tdo~I , sld_hub_inst|hub_tdo, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|hub_tdo~612_I , sld_hub_inst|hub_tdo~612, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|jtag_state_machine|state[6]~I , sld_hub_inst|jtag_state_machine|state[6], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|jtag_state_machine|state~17_I , sld_hub_inst|jtag_state_machine|state~17, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|jtag_state_machine|state[7]~I , sld_hub_inst|jtag_state_machine|state[7], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|jtag_state_machine|state~11_I , sld_hub_inst|jtag_state_machine|state~11, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|jtag_state_machine|state[4]~I , sld_hub_inst|jtag_state_machine|state[4], I2C_ALTERA, 1
instance = comp, \sld_hub_inst|jtag_state_machine|state~14_I , sld_hub_inst|jtag_state_machine|state~14, I2C_ALTERA, 1
instance = comp, \sld_hub_inst|jtag_state_machine|state[5]~I , sld_hub_inst|jtag_state_machine|state[5], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|enable_write~11_I , inst2|altsyncram_component|auto_generated|mgl_prim2|enable_write~11, I2C_ALTERA, 1
instance = comp, \SYSCLK~I , SYSCLK, I2C_ALTERA, 1
instance = comp, \inst3|altpll_component|pll , inst3|altpll_component|pll, I2C_ALTERA, 1
instance = comp, \inst3|altpll_component|_clk0~clkctrl_I , inst3|altpll_component|_clk0~clkctrl, I2C_ALTERA, 1
instance = comp, \altera_internal_jtag~TCKUTAPclkctrl_I , altera_internal_jtag~TCKUTAPclkctrl, I2C_ALTERA, 1
instance = comp, \inst|r_rom_rab_reg[0]~81_I , inst|r_rom_rab_reg[0]~81, I2C_ALTERA, 1
instance = comp, \inst|r_rom_rab_reg[1]~82_I , inst|r_rom_rab_reg[1]~82, I2C_ALTERA, 1
instance = comp, \inst|r_rom_rab_reg[2]~83_I , inst|r_rom_rab_reg[2]~83, I2C_ALTERA, 1
instance = comp, \inst|r_rom_rab_reg[3]~84_I , inst|r_rom_rab_reg[3]~84, I2C_ALTERA, 1
instance = comp, \~GND~I , ~GND, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|process1~1_I , inst2|altsyncram_component|auto_generated|mgl_prim2|process1~1, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1345_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1345, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[15]~1339_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[15]~1339, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[15]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[15], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1343_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1343, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[14]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[14], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1340_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1340, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[13]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[13], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1346_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1346, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[12]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[12], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1347_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1347, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[11]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[11], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1348_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1348, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[10]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[10], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1349_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1349, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[9]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[9], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1342_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1342, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[8]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[8], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1350_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1350, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[7]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[7], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1351_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1351, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[6]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[6], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1352_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1352, I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[5]~I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg[5], I2C_ALTERA, 1
instance = comp, \inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1353_I , inst2|altsyncram_component|auto_generated|mgl_prim2|ram_rom_data_reg~1353, I2C_ALTERA, 1
instanc