led.tan.qmsg

适用于FPGA初学者,一个流水灯的程序,用VERILOG语言写的.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_50mhz register shift_led:shift_led\|led_out\[11\] register shift_led:shift_led\|led_out\[0\] 423.91 MHz 2.359 ns Internal " "Info: Clock \"clk_50mhz\" has Internal fmax of 423.91 MHz between source register \"shift_led:shift_led\|led_out\[11\]\" and destination register \"shift_led:shift_led\|led_out\[0\]\" (period= 2.359 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.140 ns + Longest register register " "Info: + Longest register to register delay is 2.140 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_led:shift_led\|led_out\[11\] 1 REG LCFF_X53_Y1_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X53_Y1_N9; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[11\]'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "" { shift_led:shift_led|led_out[11] } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.447 ns) 0.971 ns shift_led:shift_led\|reduce_nor~127 2 COMB LCCOMB_X53_Y1_N28 1 " "Info: 2: + IC(0.524 ns) + CELL(0.447 ns) = 0.971 ns; Loc. = LCCOMB_X53_Y1_N28; Fanout = 1; COMB Node = 'shift_led:shift_led\|reduce_nor~127'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.971 ns" { shift_led:shift_led|led_out[11] shift_led:shift_led|reduce_nor~127 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.428 ns) 1.658 ns shift_led:shift_led\|reduce_nor~129 3 COMB LCCOMB_X53_Y1_N0 1 " "Info: 3: + IC(0.259 ns) + CELL(0.428 ns) = 1.658 ns; Loc. = LCCOMB_X53_Y1_N0; Fanout = 1; COMB Node = 'shift_led:shift_led\|reduce_nor~129'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.687 ns" { shift_led:shift_led|reduce_nor~127 shift_led:shift_led|reduce_nor~129 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.243 ns) + CELL(0.153 ns) 2.054 ns shift_led:shift_led\|reduce_nor~0 4 COMB LCCOMB_X53_Y1_N14 1 " "Info: 4: + IC(0.243 ns) + CELL(0.153 ns) = 2.054 ns; Loc. = LCCOMB_X53_Y1_N14; Fanout = 1; COMB Node = 'shift_led:shift_led\|reduce_nor~0'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.396 ns" { shift_led:shift_led|reduce_nor~129 shift_led:shift_led|reduce_nor~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.140 ns shift_led:shift_led\|led_out\[0\] 5 REG LCFF_X53_Y1_N15 3 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.140 ns; Loc. = LCFF_X53_Y1_N15; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[0\]'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.086 ns" { shift_led:shift_led|reduce_nor~0 shift_led:shift_led|led_out[0] } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.114 ns 52.06 % " "Info: Total cell delay = 1.114 ns ( 52.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.026 ns 47.94 % " "Info: Total interconnect delay = 1.026 ns ( 47.94 % )" {  } {  } 0}  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.140 ns" { shift_led:shift_led|led_out[11] shift_led:shift_led|reduce_nor~127 shift_led:shift_led|reduce_nor~129 shift_led:shift_led|reduce_nor~0 shift_led:shift_led|led_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.140 ns" { shift_led:shift_led|led_out[11] shift_led:shift_led|reduce_nor~127 shift_led:shift_led|reduce_nor~129 shift_led:shift_led|reduce_nor~0 shift_led:shift_led|led_out[0] } { 0.000ns 0.524ns 0.259ns 0.243ns 0.000ns } { 0.000ns 0.447ns 0.428ns 0.153ns 0.086ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50mhz destination 2.686 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_50mhz\" to destination register is 2.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk_50mhz 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50mhz'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "" { clk_50mhz } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk_50mhz~clkctrl 2 COMB CLKCTRL_G2 18 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.118 ns" { clk_50mhz clk_50mhz~clkctrl } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.548 ns) 2.686 ns shift_led:shift_led\|led_out\[0\] 3 REG LCFF_X53_Y1_N15 3 " "Info: 3: + IC(1.075 ns) + CELL(0.548 ns) = 2.686 ns; Loc. = LCFF_X53_Y1_N15; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[0\]'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "1.623 ns" { clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 55.58 % " "Info: Total cell delay = 1.493 ns ( 55.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.193 ns 44.42 % " "Info: Total interconnect delay = 1.193 ns ( 44.42 % )" {  } {  } 0}  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.686 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.686 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } { 0.000ns 0.000ns 0.118ns 1.075ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50mhz source 2.686 ns - Longest register " "Info: - Longest clock path from clock \"clk_50mhz\" to source register is 2.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk_50mhz 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50mhz'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "" { clk_50mhz } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk_50mhz~clkctrl 2 COMB CLKCTRL_G2 18 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.118 ns" { clk_50mhz clk_50mhz~clkctrl } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.548 ns) 2.686 ns shift_led:shift_led\|led_out\[11\] 3 REG LCFF_X53_Y1_N9 3 " "Info: 3: + IC(1.075 ns) + CELL(0.548 ns) = 2.686 ns; Loc. = LCFF_X53_Y1_N9; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[11\]'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "1.623 ns" { clk_50mhz~clkctrl shift_led:shift_led|led_out[11] } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 55.58 % " "Info: Total cell delay = 1.493 ns ( 55.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.193 ns 44.42 % " "Info: Total interconnect delay = 1.193 ns ( 44.42 % )" {  } {  } 0}  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.686 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.686 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[11] } { 0.000ns 0.000ns 0.118ns 1.075ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0}  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.686 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.686 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } { 0.000ns 0.000ns 0.118ns 1.075ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.686 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.686 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[11] } { 0.000ns 0.000ns 0.118ns 1.075ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns + " "Info: + Micro clock to output delay of source is 0.255 ns" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0}  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.140 ns" { shift_led:shift_led|led_out[11] shift_led:shift_led|reduce_nor~127 shift_led:shift_led|reduce_nor~129 shift_led:shift_led|reduce_nor~0 shift_led:shift_led|led_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.140 ns" { shift_led:shift_led|led_out[11] shift_led:shift_led|reduce_nor~127 shift_led:shift_led|reduce_nor~129 shift_led:shift_led|reduce_nor~0 shift_led:shift_led|led_out[0] } { 0.000ns 0.524ns 0.259ns 0.243ns 0.000ns } { 0.000ns 0.447ns 0.428ns 0.153ns 0.086ns } } } { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.686 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.686 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } { 0.000ns 0.000ns 0.118ns 1.075ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.686 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.686 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[11] } { 0.000ns 0.000ns 0.118ns 1.075ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_50mhz led_out\[10\] shift_led:shift_led\|led_out\[10\] 7.458 ns register " "Info: tco from clock \"clk_50mhz\" to destination pin \"led_out\[10\]\" through register \"shift_led:shift_led\|led_out\[10\]\" is 7.458 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50mhz source 2.686 ns + Longest register " "Info: + Longest clock path from clock \"clk_50mhz\" to source register is 2.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns clk_50mhz 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50mhz'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "" { clk_50mhz } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.063 ns clk_50mhz~clkctrl 2 COMB CLKCTRL_G2 18 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "0.118 ns" { clk_50mhz clk_50mhz~clkctrl } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.548 ns) 2.686 ns shift_led:shift_led\|led_out\[10\] 3 REG LCFF_X53_Y1_N31 3 " "Info: 3: + IC(1.075 ns) + CELL(0.548 ns) = 2.686 ns; Loc. = LCFF_X53_Y1_N31; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[10\]'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "1.623 ns" { clk_50mhz~clkctrl shift_led:shift_led|led_out[10] } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.493 ns 55.58 % " "Info: Total cell delay = 1.493 ns ( 55.58 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.193 ns 44.42 % " "Info: Total interconnect delay = 1.193 ns ( 44.42 % )" {  } {  } 0}  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.686 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.686 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[10] } { 0.000ns 0.000ns 0.118ns 1.075ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns + " "Info: + Micro clock to output delay of source is 0.255 ns" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.517 ns + Longest register pin " "Info: + Longest register to pin delay is 4.517 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_led:shift_led\|led_out\[10\] 1 REG LCFF_X53_Y1_N31 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X53_Y1_N31; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[10\]'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "" { shift_led:shift_led|led_out[10] } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.979 ns) + CELL(2.538 ns) 4.517 ns led_out\[10\] 2 PIN PIN_AA13 0 " "Info: 2: + IC(1.979 ns) + CELL(2.538 ns) = 4.517 ns; Loc. = PIN_AA13; Fanout = 0; PIN Node = 'led_out\[10\]'" {  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "4.517 ns" { shift_led:shift_led|led_out[10] led_out[10] } "NODE_NAME" } "" } } { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.538 ns 56.19 % " "Info: Total cell delay = 2.538 ns ( 56.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.979 ns 43.81 % " "Info: Total interconnect delay = 1.979 ns ( 43.81 % )" {  } {  } 0}  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "4.517 ns" { shift_led:shift_led|led_out[10] led_out[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.517 ns" { shift_led:shift_led|led_out[10] led_out[10] } { 0.000ns 1.979ns } { 0.000ns 2.538ns } } }  } 0}  } { { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "2.686 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.686 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[10] } { 0.000ns 0.000ns 0.118ns 1.075ns } { 0.000ns 0.945ns 0.000ns 0.548ns } } } { "D:/fpga practice/led/led/db/led_cmp.qrpt" "" { Report "D:/fpga practice/led/led/db/led_cmp.qrpt" Compiler "led" "UNKNOWN" "V1" "D:/fpga practice/led/led/db/led.quartus_db" { Floorplan "D:/fpga practice/led/led/" "" "4.517 ns" { shift_led:shift_led|led_out[10] led_out[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.517 ns" { shift_led:shift_led|led_out[10] led_out[10] } { 0.000ns 1.979ns } { 0.000ns 2.538ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 19 13:16:16 2008 " "Info: Processing ended: Fri Sep 19 13:16:16 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}