led.map.qmsg

适用于FPGA初学者,一个流水灯的程序,用VERILOG语言写的.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 19 13:15:52 2008 " "Info: Processing started: Fri Sep 19 13:15:52 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off led -c led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led -c led" {  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/altera/71/quartus/led.v " "Warning: Can't analyze file -- file E:/altera/71/quartus/led.v is missing" {  } {  } 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITHOUT_RANGE" "led_out led.v(42) " "Warning: Verilog HDL warning at led.v(42): using specified range for net, port, or variable \"led_out\" that was previously declared without a range specification" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 42 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "led.v 3 3 " "Info: Using design file led.v, which is not specified as a design file for the current project, but contains definitions for 3 design units and 3 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 led " "Info: Found entity 1: led" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 1 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 divider_5hz " "Info: Found entity 2: divider_5hz" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 shift_led " "Info: Found entity 3: shift_led" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 38 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "led " "Info: Elaborating entity \"led\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shift_led shift_led:shift_led " "Info: Elaborating entity \"shift_led\" for hierarchy \"shift_led:shift_led\"" {  } { { "led.v" "shift_led" { Text "D:/fpga practice/led/led/led.v" 7 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 led.v(47) " "Warning: Verilog HDL assignment warning at led.v(47): truncated value with size 32 to match size of target (18)" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 47 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 led.v(51) " "Warning: Verilog HDL assignment warning at led.v(51): truncated value with size 32 to match size of target (18)" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 51 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divider_5hz divider_5hz:divider_5hz " "Info: Elaborating entity \"divider_5hz\" for hierarchy \"divider_5hz:divider_5hz\"" {  } { { "led.v" "divider_5hz" { Text "D:/fpga practice/led/led/led.v" 8 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 led.v(23) " "Warning: Verilog HDL assignment warning at led.v(23): truncated value with size 32 to match size of target (26)" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 led.v(25) " "Warning: Verilog HDL assignment warning at led.v(25): truncated value with size 32 to match size of target (26)" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 25 0 0 } }  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "led.v" "" { Text "D:/fpga practice/led/led/led.v" 40 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "45 " "Info: Implemented 45 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "25 " "Info: Implemented 25 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 19 13:15:53 2008 " "Info: Processing ended: Fri Sep 19 13:15:53 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}