led.tan.rpt

适用于FPGA初学者,一个流水灯的程序,用VERILOG语言写的.

; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[13] ; shift_led:shift_led|led_out[0]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 1.219 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[16] ; shift_led:shift_led|led_out[0]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 1.041 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[5]  ; shift_led:shift_led|led_out[6]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.889 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[3]  ; shift_led:shift_led|led_out[4]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.883 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[13] ; shift_led:shift_led|led_out[14] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.876 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[9]  ; shift_led:shift_led|led_out[10] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.875 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[8]  ; shift_led:shift_led|led_out[9]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.873 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[4]  ; shift_led:shift_led|led_out[5]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.870 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[17] ; shift_led:shift_led|led_out[0]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.866 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[1]  ; shift_led:shift_led|led_out[2]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.842 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[15] ; shift_led:shift_led|led_out[16] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.748 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[2]  ; shift_led:shift_led|led_out[3]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.737 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[0]  ; shift_led:shift_led|led_out[1]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.702 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[7]  ; shift_led:shift_led|led_out[8]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.689 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[12] ; shift_led:shift_led|led_out[13] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.687 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[6]  ; shift_led:shift_led|led_out[7]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.683 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[11] ; shift_led:shift_led|led_out[12] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.675 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[10] ; shift_led:shift_led|led_out[11] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.563 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[14] ; shift_led:shift_led|led_out[15] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.561 ns                ;
; N/A   ; Restricted to 464.04 MHz ( period = 2.155 ns ) ; shift_led:shift_led|led_out[16] ; shift_led:shift_led|led_out[17] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.548 ns                ;
+-------+------------------------------------------------+---------------------------------+---------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------------------------------+
; tco                                                                                            ;
+-------+--------------+------------+---------------------------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From                            ; To          ; From Clock ;
+-------+--------------+------------+---------------------------------+-------------+------------+
; N/A   ; None         ; 7.458 ns   ; shift_led:shift_led|led_out[10] ; led_out[10] ; clk_50mhz  ;
; N/A   ; None         ; 7.422 ns   ; shift_led:shift_led|led_out[15] ; led_out[15] ; clk_50mhz  ;
; N/A   ; None         ; 7.395 ns   ; shift_led:shift_led|led_out[9]  ; led_out[9]  ; clk_50mhz  ;
; N/A   ; None         ; 7.200 ns   ; shift_led:shift_led|led_out[14] ; led_out[14] ; clk_50mhz  ;
; N/A   ; None         ; 7.088 ns   ; shift_led:shift_led|led_out[12] ; led_out[12] ; clk_50mhz  ;
; N/A   ; None         ; 7.077 ns   ; shift_led:shift_led|led_out[8]  ; led_out[8]  ; clk_50mhz  ;
; N/A   ; None         ; 7.063 ns   ; shift_led:shift_led|led_out[13] ; led_out[13] ; clk_50mhz  ;
; N/A   ; None         ; 6.917 ns   ; shift_led:shift_led|led_out[16] ; led_out[16] ; clk_50mhz  ;
; N/A   ; None         ; 6.887 ns   ; shift_led:shift_led|led_out[11] ; led_out[11] ; clk_50mhz  ;
; N/A   ; None         ; 6.862 ns   ; shift_led:shift_led|led_out[17] ; led_out[17] ; clk_50mhz  ;
; N/A   ; None         ; 6.856 ns   ; shift_led:shift_led|led_out[5]  ; led_out[5]  ; clk_50mhz  ;
; N/A   ; None         ; 6.810 ns   ; shift_led:shift_led|led_out[1]  ; led_out[1]  ; clk_50mhz  ;
; N/A   ; None         ; 6.807 ns   ; shift_led:shift_led|led_out[0]  ; led_out[0]  ; clk_50mhz  ;
; N/A   ; None         ; 6.800 ns   ; shift_led:shift_led|led_out[4]  ; led_out[4]  ; clk_50mhz  ;
; N/A   ; None         ; 6.799 ns   ; shift_led:shift_led|led_out[6]  ; led_out[6]  ; clk_50mhz  ;
; N/A   ; None         ; 6.797 ns   ; shift_led:shift_led|led_out[3]  ; led_out[3]  ; clk_50mhz  ;
; N/A   ; None         ; 6.797 ns   ; shift_led:shift_led|led_out[2]  ; led_out[2]  ; clk_50mhz  ;
; N/A   ; None         ; 6.571 ns   ; shift_led:shift_led|led_out[7]  ; led_out[7]  ; clk_50mhz  ;
+-------+--------------+------------+---------------------------------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Sep 19 13:16:16 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led -c led --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_50mhz" is an undefined clock
Info: Clock "clk_50mhz" has Internal fmax of 423.91 MHz between source register "shift_led:shift_led|led_out[11]" and destination register "shift_led:shift_led|led_out[0]" (period= 2.359 ns)
    Info: + Longest register to register delay is 2.140 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X53_Y1_N9; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[11]'
        Info: 2: + IC(0.524 ns) + CELL(0.447 ns) = 0.971 ns; Loc. = LCCOMB_X53_Y1_N28; Fanout = 1; COMB Node = 'shift_led:shift_led|reduce_nor~127'
        Info: 3: + IC(0.259 ns) + CELL(0.428 ns) = 1.658 ns; Loc. = LCCOMB_X53_Y1_N0; Fanout = 1; COMB Node = 'shift_led:shift_led|reduce_nor~129'
        Info: 4: + IC(0.243 ns) + CELL(0.153 ns) = 2.054 ns; Loc. = LCCOMB_X53_Y1_N14; Fanout = 1; COMB Node = 'shift_led:shift_led|reduce_nor~0'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 2.140 ns; Loc. = LCFF_X53_Y1_N15; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[0]'
        Info: Total cell delay = 1.114 ns ( 52.06 % )
        Info: Total interconnect delay = 1.026 ns ( 47.94 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk_50mhz" to destination register is 2.686 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50mhz'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'
            Info: 3: + IC(1.075 ns) + CELL(0.548 ns) = 2.686 ns; Loc. = LCFF_X53_Y1_N15; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[0]'
            Info: Total cell delay = 1.493 ns ( 55.58 % )
            Info: Total interconnect delay = 1.193 ns ( 44.42 % )
        Info: - Longest clock path from clock "clk_50mhz" to source register is 2.686 ns
            Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50mhz'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'
            Info: 3: + IC(1.075 ns) + CELL(0.548 ns) = 2.686 ns; Loc. = LCFF_X53_Y1_N9; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[11]'
            Info: Total cell delay = 1.493 ns ( 55.58 % )
            Info: Total interconnect delay = 1.193 ns ( 44.42 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk_50mhz" to destination pin "led_out[10]" through register "shift_led:shift_led|led_out[10]" is 7.458 ns
    Info: + Longest clock path from clock "clk_50mhz" to source register is 2.686 ns
        Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50mhz'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.063 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'
        Info: 3: + IC(1.075 ns) + CELL(0.548 ns) = 2.686 ns; Loc. = LCFF_X53_Y1_N31; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[10]'
        Info: Total cell delay = 1.493 ns ( 55.58 % )
        Info: Total interconnect delay = 1.193 ns ( 44.42 % )
    Info: + Micro clock to output delay of source is 0.255 ns
    Info: + Longest register to pin delay is 4.517 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X53_Y1_N31; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[10]'
        Info: 2: + IC(1.979 ns) + CELL(2.538 ns) = 4.517 ns; Loc. = PIN_AA13; Fanout = 0; PIN Node = 'led_out[10]'
        Info: Total cell delay = 2.538 ns ( 56.19 % )
        Info: Total interconnect delay = 1.979 ns ( 43.81 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Sep 19 13:16:16 2008
    Info: Elapsed time: 00:00:00