led.map.rpt

适用于FPGA初学者,一个流水灯的程序,用VERILOG语言写的.

+--------------------------------------------------------------------+--------------+---------------+


+-------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                          ;
+----------------------------------+-----------------+-----------+--------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path   ;
+----------------------------------+-----------------+-----------+--------------------------------+
; led.v                            ; yes             ; Other     ; D:/fpga practice/led/led/led.v ;
+----------------------------------+-----------------+-----------+--------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+---------------------------------------------+-----------+
; Resource                                    ; Usage     ;
+---------------------------------------------+-----------+
; Total combinational functions               ; 7         ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 5         ;
;     -- 3 input functions                    ; 1         ;
;     -- <=2 input functions                  ; 1         ;
;         -- Combinational cells for routing  ; 0         ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 7         ;
;     -- arithmetic mode                      ; 0         ;
; Total registers                             ; 18        ;
; I/O pins                                    ; 20        ;
; Maximum fan-out node                        ; clk_50mhz ;
; Maximum fan-out                             ; 18        ;
; Total fan-out                               ; 96        ;
; Average fan-out                             ; 2.13      ;
+---------------------------------------------+-----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                               ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name      ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+
; |led                       ; 7 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 20   ; 0            ; |led                     ;
;    |shift_led:shift_led|   ; 7 (7)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |led|shift_led:shift_led ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 18    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 18    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; shift_led:shift_led|led_out[0]         ; 3       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/fpga practice/led/led/led.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Sep 19 13:15:52 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led -c led
Warning: Can't analyze file -- file E:/altera/71/quartus/led.v is missing
Warning: Verilog HDL warning at led.v(42): using specified range for net, port, or variable "led_out" that was previously declared without a range specification
Info: Using design file led.v, which is not specified as a design file for the current project, but contains definitions for 3 design units and 3 entities in project
    Info: Found entity 1: led
    Info: Found entity 2: divider_5hz
    Info: Found entity 3: shift_led
Info: Elaborating entity "led" for the top level hierarchy
Info: Elaborating entity "shift_led" for hierarchy "shift_led:shift_led"
Warning: Verilog HDL assignment warning at led.v(47): truncated value with size 32 to match size of target (18)
Warning: Verilog HDL assignment warning at led.v(51): truncated value with size 32 to match size of target (18)
Info: Elaborating entity "divider_5hz" for hierarchy "divider_5hz:divider_5hz"
Warning: Verilog HDL assignment warning at led.v(23): truncated value with size 32 to match size of target (26)
Warning: Verilog HDL assignment warning at led.v(25): truncated value with size 32 to match size of target (26)
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 45 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 18 output pins
    Info: Implemented 25 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Fri Sep 19 13:15:53 2008
    Info: Elapsed time: 00:00:01