counter.vhd

来自「自己收集的VHDL例程代码」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Counter is
port
(clk:in std_logic;
clear:in std_logic;
IncreaseA,IncreaseB:in std_logic;
ScoreA,ScoreB:buffer integer range 0 to 21
);
end Counter;

architecture Count of Counter is
begin
	process(clk,clear)
	begin
		if clear='1' then
		ScoreA<=0;
		ScoreB<=0;
		elsif falling_edge(clk) then
		if IncreaseA='1' then
			ScoreA<=ScoreA+1;
		elsif IncreaseB='1' then
			ScoreB<=ScoreB+1;
		end if;
	end if;
	end process;
end Count;