📄 statemachine.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Statemachine is
port
(clk:in std_logic;
reset:in std_logic;
StartA,hitA,StartB,hitB:in std_logic;
ScoreA,ScoreB:integer range 0 to 21;
clear,IncreaseA,IncreaseB:out std_logic;
Tablelight:out std_logic_vector(0 to 8);
Awin,Bwin:out std_logic
);
end Statemachine;
architecture behavior of Statemachine is
Type State_type is(WaitState,AtoB,BtoA,AScore,BScore,FinalResult);
Signal State:State_type;
signal TableState:integer range 0 to 8;
begin
process(clk,reset)
begin
if reset='1' then
State<=WaitState;
clear<='1';
Awin<='0';
Bwin<='0';
elsif rising_edge(clk) then
case State is
when WaitState=>
clear<='0';
IncreaseA<='0';
IncreaseB<='0';
if ((ScoreA=21)or(ScoreB=21))then
State<=FinalResult;
else
if StartA='1' then
State<=AtoB;
TableState<=0;
else
if StartB='1' then
State<=BtoA;
TableState<=8;
else
State<=WaitState;
end if;
end if;
end if;
when AtoB=>
if hitB='1' then
if TableState<=4 then
State<=AScore;
else
State<=BtoA;
end if;
else
if TableState=8 then
State<=AScore;
else
TableState<=TableState+1;
end if;
end if;
when BtoA=>
if hitA='1' then
if TableState>=4 then
State<=BScore;
else
State<=AtoB;
end if;
else
if TableState=0 then
State<=BScore;
else
TableState<=TableState-1;
end if;
end if;
when AScore=>
IncreaseA<='1';
State<=WaitState;
when BScore=>
IncreaseB<='1';
State<=WaitState;
When FinalResult=>
if(ScoreA=21) then
Awin<='1';
else
Bwin<='1';
end if;
when others=>
State<=WaitState;
end case;
end if;
end process;
process(clk)
begin
if falling_edge(clk) then
if((State=AtoB)or(State=BtoA)) then
Case TableState is
when 0=>TableLight<="100000000";
when 1=>TableLight<="010000000";
when 2=>TableLight<="001000000";
when 3=>TableLight<="000100000";
when 4=>TableLight<="000010000";
when 5=>TableLight<="000001000";
when 6=>TableLight<="000000100";
when 7=>TableLight<="000000010";
when 8=>TableLight<="000000001";
when others=>TableLight<="000000000";
end case;
else
TableLight<="000000000";
end if;
end if;
end process;
end;
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