traffic.v

利用vhdl编写的模拟交通灯的程序

module traffic(Clock,Reset,Strait_A_Out,Block_A_Out,Turn_A_Out,Strait_B_Out,Block_B_Out,Turn_B_Out,Count_Down_LCD,Road_sign,Ctr);
//************************  Initial  *************************
input Clock,Reset; //1KHZ时钟信号和复位信号
output [6:0] Count_Down_LCD;
output Ctr;
output Strait_A_Out,Block_A_Out,Turn_A_Out,Strait_B_Out,Block_B_Out,Turn_B_Out;
output [13:0] Road_sign;

reg Clock_4Hz,LCD;
reg [4:0] Count_4Hz;
reg [1:0] Count_1Hz;
reg Clock_1Hz;
reg [2:0] Count_Down;
reg [6:0] Count_Down_LCD;

//wire [13:0] Road_sign
reg [13:0] q;
reg Strait_A,Block_A,Turn_A,Strait_B,Block_B,Turn_B;

reg [1:0] State;
reg Blink;
reg [2:0] Count;

assign Ctr=1'b1;
assign Strait_A_Out=Strait_A & (Clock_4Hz|Blink);
assign Strait_B_Out=Strait_B & (Clock_4Hz|Blink);
assign Block_A_Out=Block_A & (Clock_4Hz|Blink);
assign Block_B_Out=Block_B & (Clock_4Hz|Blink);
assign Turn_A_Out=Turn_A & (Clock_4Hz|Blink);
assign Turn_B_Out=Turn_B & (Clock_4Hz|Blink);

assign Road_sign[13:7] = q[13:7];
assign Road_sign[6:0] =  (~q[6:0]) & {7{Clock_4Hz|Blink}};
parameter Strait_Block=0, Block_Turn=1, Turn_Block=2, Block_Strait=3;

//*************  Generate 4Hz Clock Signal from 1kHz Clock Signal  **********
always @(posedge Clock)
	begin
		Count_4Hz = Count_4Hz-1;
		if(Count_4Hz==0)
			begin
				Clock_4Hz = ~Clock_4Hz;	//Generate 4Hz clock signal
			end
	end

//*************  Generate 1Hz Clock Signal from 4Hz Clock Signal  ***********
always @(posedge Clock_4Hz)
	begin
		Count_1Hz = Count_1Hz-1;
		if(Count_1Hz==0) Clock_1Hz = ~Clock_1Hz;	//Generate 1Hz clock signal
	end

//****************************  Main Program  *******************************
always @(posedge Clock_1Hz)
	begin
		if(Reset==1)
			begin
				State=Strait_Block;
				Count_Down=0;
				Strait_A=1; Block_A=1; Turn_A=1;
				Strait_B=1; Block_B=1; Turn_B=1;
				Count_Down_LCD[6:0]=7'b1111111;
				Blink=1;
			end
		else
			begin
				Count_Down=Count_Down-1;
				case (State)
					Strait_Block:	begin
										Strait_A=1; Block_A=0; Turn_A=0;
										Strait_B=0; Block_B=1; Turn_B=0;
										if(Count_Down==0) State=Block_Turn;	
									end
					Block_Turn:		begin
										Strait_A=0; Block_A=1; Turn_A=0;
										Strait_B=0; Block_B=0; Turn_B=1;
										if(Count_Down==0) State=Turn_Block;
									end
					Turn_Block:		begin
										Strait_A=0; Block_A=0; Turn_A=1;
										Strait_B=0; Block_B=1; Turn_B=0;
										if(Count_Down==0) State=Block_Strait;
									end
					Block_Strait:	begin
										Strait_A=0; Block_A=1; Turn_A=0;
										Strait_B=1; Block_B=0; Turn_B=0;
										if(Count_Down==0) State=Strait_Block;
									end				
				endcase
				case(Count_Down)
					3'b000:	Count_Down_LCD[6:0]=7'b0000110;	//1
					3'b001:	Count_Down_LCD[6:0]=7'b1011011;	//2
					3'b010:	Count_Down_LCD[6:0]=7'b1001111;	//3
					3'b011:	Count_Down_LCD[6:0]=7'b1100110;	//4
					3'b100:	Count_Down_LCD[6:0]=7'b1101101; //5
					3'b101:	Count_Down_LCD[6:0]=7'b1111101;	//6
					3'b110:	Count_Down_LCD[6:0]=7'b0000111;	//7
					3'b111:	Count_Down_LCD[6:0]=7'b1111111;	//8
				endcase
				if (Count_Down>=3) Blink=1;
				else Blink=0;
			end
	end
	
always @(posedge Clock)
	begin
		if (Reset==1)
			q=14'b0000000-0000000;
		else begin
			if (Count==3'b111)
				Count=3'b000;
			else
				Count=Count+1;

			case ({Strait_A, Block_A, Turn_A})
				3'b100: //Strait
					case (Count)
						3'b000: q=14'b10000001111111;
						3'b001: q=14'b01000001111111;
						3'b010: q=14'b00100001011111;
						3'b011: q=14'b00010000000000;
						3'b100: q=14'b00001001011111;
						3'b101: q=14'b00000101111111;
						3'b110: q=14'b00000011111111;						
					endcase
				3'b010://Block
					case (Count)
						3'b000: q=14'b10000000111110;
						3'b001: q=14'b01000001011101;
						3'b010: q=14'b00100001101011;
						3'b011: q=14'b00010001110111;
						3'b100: q=14'b00001001101011;
						3'b101: q=14'b00000101011101;
						3'b110: q=14'b00000010111110;						
					endcase
				3'b001://Turn
					case (Count)
						3'b000: q=14'b10000001111111;
						3'b001: q=14'b01000001111111;
						3'b010: q=14'b00100001110000;
						3'b011: q=14'b00010001101111;
						3'b100: q=14'b00001001101111;
						3'b101: q=14'b00000101000111;
						3'b110: q=14'b00000011101111;						
					endcase
			endcase
		end
	end
endmodule