traffic.tan.qmsg

利用vhdl编写的模拟交通灯的程序

{ "Info" "ITDB_TH_RESULT" "State\[0\] Reset Clock 2.779 ns register " "Info: th for register State\[0\] (data pin = Reset, clock pin = Clock) is 2.779 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 11.599 ns + Longest register " "Info: + Longest clock path from clock Clock to destination register is 11.599 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clock 1 CLK PIN_152 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 23; CLK Node = 'Clock'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "" { Clock } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.935 ns) 3.105 ns Clock_4Hz 2 REG LC_X8_Y9_N2 17 " "Info: 2: + IC(0.701 ns) + CELL(0.935 ns) = 3.105 ns; Loc. = LC_X8_Y9_N2; Fanout = 17; REG Node = 'Clock_4Hz'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "1.636 ns" { Clock Clock_4Hz } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.656 ns) + CELL(0.935 ns) 7.696 ns Clock_1Hz 3 REG LC_X8_Y10_N5 20 " "Info: 3: + IC(3.656 ns) + CELL(0.935 ns) = 7.696 ns; Loc. = LC_X8_Y10_N5; Fanout = 20; REG Node = 'Clock_1Hz'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "4.591 ns" { Clock_4Hz Clock_1Hz } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.192 ns) + CELL(0.711 ns) 11.599 ns State\[0\] 4 REG LC_X11_Y9_N2 8 " "Info: 4: + IC(3.192 ns) + CELL(0.711 ns) = 11.599 ns; Loc. = LC_X11_Y9_N2; Fanout = 8; REG Node = 'State\[0\]'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "3.903 ns" { Clock_1Hz State[0] } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 72 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 34.92 % " "Info: Total cell delay = 4.050 ns ( 34.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.549 ns 65.08 % " "Info: Total interconnect delay = 7.549 ns ( 65.08 % )" {  } {  } 0}  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "11.599 ns" { Clock Clock_4Hz Clock_1Hz State[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 72 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.835 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.835 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Reset 1 PIN PIN_1 38 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 38; PIN Node = 'Reset'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "" { Reset } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.057 ns) + CELL(0.309 ns) 8.835 ns State\[0\] 2 REG LC_X11_Y9_N2 8 " "Info: 2: + IC(7.057 ns) + CELL(0.309 ns) = 8.835 ns; Loc. = LC_X11_Y9_N2; Fanout = 8; REG Node = 'State\[0\]'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "7.366 ns" { Reset State[0] } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 72 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns 20.12 % " "Info: Total cell delay = 1.778 ns ( 20.12 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.057 ns 79.88 % " "Info: Total interconnect delay = 7.057 ns ( 79.88 % )" {  } {  } 0}  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "8.835 ns" { Reset State[0] } "NODE_NAME" } } }  } 0}  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "11.599 ns" { Clock Clock_4Hz Clock_1Hz State[0] } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "8.835 ns" { Reset State[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "Clock Road_sign\[9\] q\[9\] 7.420 ns register " "Info: Minimum tco from clock Clock to destination pin Road_sign\[9\] through register q\[9\] is 7.420 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 2.881 ns + Shortest register " "Info: + Shortest clock path from clock Clock to source register is 2.881 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns Clock 1 CLK PIN_152 23 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 23; CLK Node = 'Clock'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "" { Clock } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.701 ns) + CELL(0.711 ns) 2.881 ns q\[9\] 2 REG LC_X12_Y8_N5 2 " "Info: 2: + IC(0.701 ns) + CELL(0.711 ns) = 2.881 ns; Loc. = LC_X12_Y8_N5; Fanout = 2; REG Node = 'q\[9\]'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "1.412 ns" { Clock q[9] } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 130 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.67 % " "Info: Total cell delay = 2.180 ns ( 75.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.701 ns 24.33 % " "Info: Total interconnect delay = 0.701 ns ( 24.33 % )" {  } {  } 0}  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "2.881 ns" { Clock q[9] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 130 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.315 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.315 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q\[9\] 1 REG LC_X12_Y8_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N5; Fanout = 2; REG Node = 'q\[9\]'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "" { q[9] } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 130 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.207 ns) + CELL(2.108 ns) 4.315 ns Road_sign\[9\] 2 PIN PIN_85 0 " "Info: 2: + IC(2.207 ns) + CELL(2.108 ns) = 4.315 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'Road_sign\[9\]'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "4.315 ns" { q[9] Road_sign[9] } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 48.85 % " "Info: Total cell delay = 2.108 ns ( 48.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.207 ns 51.15 % " "Info: Total interconnect delay = 2.207 ns ( 51.15 % )" {  } {  } 0}  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "4.315 ns" { q[9] Road_sign[9] } "NODE_NAME" } } }  } 0}  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "2.881 ns" { Clock q[9] } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "4.315 ns" { q[9] Road_sign[9] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 07 15:51:33 2006 " "Info: Processing ended: Wed Jun 07 15:51:33 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}