traffic.fit.qmsg

利用vhdl编写的模拟交通灯的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 07 15:51:20 2006 " "Info: Processing started: Wed Jun 07 15:51:20 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off traffic -c traffic " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off traffic -c traffic" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "traffic EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design traffic" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation -- maximum Fitter effort will be used to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "Clock Global clock in PIN 152 " "Info: Automatically promoted signal Clock to use Global clock in PIN 152" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "Clock_1Hz Global clock " "Info: Automatically promoted some destinations of signal Clock_1Hz to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Clock_1Hz " "Info: Destination Clock_1Hz may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 60 -1 0 } }  } 0}  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 60 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "Clock_4Hz Global clock " "Info: Automatically promoted some destinations of signal Clock_4Hz to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Clock_4Hz " "Info: Destination Clock_4Hz may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 49 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Strait_A_Out~1 " "Info: Destination Strait_A_Out~1 may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Block_A_Out~0 " "Info: Destination Block_A_Out~0 may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Turn_A_Out~0 " "Info: Destination Turn_A_Out~0 may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Strait_B_Out~0 " "Info: Destination Strait_B_Out~0 may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Block_B_Out~0 " "Info: Destination Block_B_Out~0 may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Turn_B_Out~0 " "Info: Destination Turn_B_Out~0 may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 7 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Road_sign~0 " "Info: Destination Road_sign~0 may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Road_sign~1 " "Info: Destination Road_sign~1 may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Road_sign~2 " "Info: Destination Road_sign~2 may be non-global or may not use global clock" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 9 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 49 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.860 ns register register " "Info: Estimated most critical path is register to register delay of 2.860 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Strait_A 1 REG LAB_X11_Y8 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y8; Fanout = 9; REG Node = 'Strait_A'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "" { Strait_A } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 72 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.442 ns) 0.653 ns Mux~1952 2 COMB LAB_X11_Y8 15 " "Info: 2: + IC(0.211 ns) + CELL(0.442 ns) = 0.653 ns; Loc. = LAB_X11_Y8; Fanout = 15; COMB Node = 'Mux~1952'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "0.653 ns" { Strait_A Mux~1952 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.982 ns) + CELL(1.225 ns) 2.860 ns q\[13\] 3 REG LAB_X7_Y8 3 " "Info: 3: + IC(0.982 ns) + CELL(1.225 ns) = 2.860 ns; Loc. = LAB_X7_Y8; Fanout = 3; REG Node = 'q\[13\]'" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "2.207 ns" { Mux~1952 q[13] } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 130 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.667 ns 58.29 % " "Info: Total cell delay = 1.667 ns ( 58.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.193 ns 41.71 % " "Info: Total interconnect delay = 1.193 ns ( 41.71 % )" {  } {  } 0}  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "2.860 ns" { Strait_A Mux~1952 q[13] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "1 " "Info: Fitter routing operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "Ctr VCC " "Info: Pin Ctr has VCC driving its datain port" {  } { { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" "" "" { Text "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.vhd" 10 -1 0 } } { "g:/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus41/bin/Assignment Editor.qase" 1 { { 0 "Ctr" } } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" "" "" { Report "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic_cmp.qrpt" Compiler "traffic" "UNKNOWN" "V1" "E:/Documents and Settings/橘子弟弟/桌面/traffic/db/traffic.quartus_db" { Floorplan "" "" "" { Ctr } "NODE_NAME" } } } { "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.fld" "" "" { Floorplan "E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.fld" "" "" { Ctr } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 07 15:51:29 2006 " "Info: Processing ended: Wed Jun 07 15:51:29 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}