traffic.map.rpt

利用vhdl编写的模拟交通灯的程序

+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 12    ;
; Number of synthesis-generated cells                    ; 90    ;
; Number of WYSIWYG LUTs                                 ; 12    ;
; Number of synthesis-generated LUTs                     ; 84    ;
; Number of WYSIWYG registers                            ; 12    ;
; Number of synthesis-generated registers                ; 33    ;
; Number of cells with combinational logic only          ; 57    ;
; Number of cells with registers only                    ; 6     ;
; Number of cells with combinational logic and registers ; 39    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 7     ;
; Number of registers using Synchronous Load   ; 7     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 5     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
traffic
 |-- lpm_counter:Count_4Hz_rtl_0
      |-- cntr_037:auto_generated


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                      ;
+----------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------+
; Compilation Hierarchy Node       ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                          ;
+----------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------+
; |traffic                         ; 102 (97)    ; 45           ; 0           ; 30   ; 0            ; 57 (57)      ; 6 (6)             ; 39 (34)          ; 5 (0)           ; |traffic                                                     ;
;    |lpm_counter:Count_4Hz_rtl_0| ; 5 (0)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (0)            ; 5 (0)           ; |traffic|lpm_counter:Count_4Hz_rtl_0                         ;
;       |cntr_037:auto_generated|  ; 5 (5)       ; 5            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 5 (5)           ; |traffic|lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated ;
+----------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Documents and Settings/橘子弟弟/桌面/traffic/traffic.map.eqn.


+-----------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                            ;
+-----------------------------------------------------------------+-----------------+
; File Name                                                       ; Used in Netlist ;
+-----------------------------------------------------------------+-----------------+
; traffic.vhd                                                     ; yes             ;
; g:/quartus41/libraries/megafunctions/lpm_counter.tdf            ; yes             ;
; g:/quartus41/libraries/megafunctions/lpm_constant.inc           ; yes             ;
; E:/Documents and Settings/橘子弟弟/桌面/traffic/db/cntr_037.tdf ; yes             ;
+-----------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 102     ;
; Total combinational functions     ; 96      ;
; Total 4-input functions           ; 44      ;
; Total 3-input functions           ; 36      ;
; Total 2-input functions           ; 11      ;
; Total 1-input functions           ; 5       ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 45      ;
; Total logic cells in carry chains ; 5       ;
; I/O pins                          ; 30      ;
; Maximum fan-out node              ; Reset   ;
; Maximum fan-out                   ; 38      ;
; Total fan-out                     ; 419     ;
; Average fan-out                   ; 3.17    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed Jun 07 15:51:16 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off traffic -c traffic
Info: Found 2 design units, including 1 entities, in source file traffic.vhd
    Info: Found design unit 1: traffic-traffic
    Info: Found entity 1: traffic
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: Count_4Hz[0]~0
Info: Found 1 design units, including 1 entities, in source file g:/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_037.tdf
    Info: Found entity 1: cntr_037
Warning: Output pins are stuck at VCC or GND
    Warning: Pin Ctr stuck at VCC
Info: Implemented 132 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 28 output pins
    Info: Implemented 102 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Jun 07 15:51:19 2006
    Info: Elapsed time: 00:00:03