traffic.map.eqn

利用vhdl编写的模拟交通灯的程序

--Strait_A is Strait_A
--operation mode is normal

Strait_A_lut_out = Reset # !State[0] & !State[1];
Strait_A = DFFEA(Strait_A_lut_out, Clock_1Hz, VCC, , , , );


--Clock_4Hz is Clock_4Hz
--operation mode is normal

Clock_4Hz_lut_out = !Clock_4Hz;
Clock_4Hz = DFFEA(Clock_4Hz_lut_out, Clock, VCC, , A1L39, , );


--Blink is Blink
--operation mode is normal

Blink_lut_out = Reset # Count_Down[2] # Count_Down[1] & Count_Down[0];
Blink = DFFEA(Blink_lut_out, Clock_1Hz, VCC, , , , );


--A1L521 is Strait_A_Out~1
--operation mode is normal

A1L521 = Strait_A & (Clock_4Hz # Blink);


--Block_A is Block_A
--operation mode is normal

Block_A_lut_out = Reset # State[0];
Block_A = DFFEA(Block_A_lut_out, Clock_1Hz, VCC, , , , );


--A1L5 is Block_A_Out~0
--operation mode is normal

A1L5 = Block_A & (Clock_4Hz # Blink);


--Turn_A is Turn_A
--operation mode is normal

Turn_A_lut_out = Reset # State[1] & !State[0];
Turn_A = DFFEA(Turn_A_lut_out, Clock_1Hz, VCC, , , , );


--A1L131 is Turn_A_Out~0
--operation mode is normal

A1L131 = Turn_A & (Clock_4Hz # Blink);


--Strait_B is Strait_B
--operation mode is normal

Strait_B_lut_out = Reset # State[0] & State[1];
Strait_B = DFFEA(Strait_B_lut_out, Clock_1Hz, VCC, , , , );


--A1L821 is Strait_B_Out~0
--operation mode is normal

A1L821 = Strait_B & (Clock_4Hz # Blink);


--Block_B is Block_B
--operation mode is normal

Block_B_lut_out = Reset # !State[0];
Block_B = DFFEA(Block_B_lut_out, Clock_1Hz, VCC, , , , );


--A1L8 is Block_B_Out~0
--operation mode is normal

A1L8 = Block_B & (Clock_4Hz # Blink);


--Turn_B is Turn_B
--operation mode is normal

Turn_B_lut_out = Reset # State[0] & !State[1];
Turn_B = DFFEA(Turn_B_lut_out, Clock_1Hz, VCC, , , , );


--A1L431 is Turn_B_Out~0
--operation mode is normal

A1L431 = Turn_B & (Clock_4Hz # Blink);


--A1L93Q is Count_Down_LCD[6]~reg0
--operation mode is normal

A1L93Q_lut_out = Count_Down[0] # Reset # Count_Down[1] $ Count_Down[2];
A1L93Q = DFFEA(A1L93Q_lut_out, Clock_1Hz, VCC, , , , );


--A1L73Q is Count_Down_LCD[5]~reg0
--operation mode is normal

A1L73Q_lut_out = Reset # Count_Down[1] & Count_Down[0] # !Count_Down[1] & Count_Down[2];
A1L73Q = DFFEA(A1L73Q_lut_out, Clock_1Hz, VCC, , , , );


--A1L53Q is Count_Down_LCD[4]~reg0
--operation mode is normal

A1L53Q_lut_out = Reset # Count_Down[0] & (Count_Down[2] # !Count_Down[1]);
A1L53Q = DFFEA(A1L53Q_lut_out, Clock_1Hz, VCC, , , , );


--A1L33Q is Count_Down_LCD[3]~reg0
--operation mode is normal

A1L33Q_lut_out = Reset # Count_Down[0] & (Count_Down[2] # !Count_Down[1]) # !Count_Down[0] & (Count_Down[1] $ Count_Down[2]);
A1L33Q = DFFEA(A1L33Q_lut_out, Clock_1Hz, VCC, , , , );


--A1L13Q is Count_Down_LCD[2]~reg0
--operation mode is normal

A1L13Q_lut_out = Reset # Count_Down[1] # Count_Down[2] # !Count_Down[0];
A1L13Q = DFFEA(A1L13Q_lut_out, Clock_1Hz, VCC, , , , );


--A1L92Q is Count_Down_LCD[1]~reg0
--operation mode is normal

A1L92Q_lut_out = Reset # Count_Down[1] # !Count_Down[2];
A1L92Q = DFFEA(A1L92Q_lut_out, Clock_1Hz, VCC, , , , );


--A1L72Q is Count_Down_LCD[0]~reg0
--operation mode is normal

A1L72Q_lut_out = Count_Down[2] # Reset # Count_Down[0] $ Count_Down[1];
A1L72Q = DFFEA(A1L72Q_lut_out, Clock_1Hz, VCC, , , , );


--q[13] is q[13]
--operation mode is normal

q[13]_lut_out = A1L14 & A1L24 & Count[2] # !A1L14 & (A1L24 # !Count[2]);
q[13]_sload_eqn = (A1L15 & q[13]) # (!A1L15 & q[13]_lut_out);
q[13]_reg_input = q[13]_sload_eqn & !Reset;
q[13] = DFFEA(q[13]_reg_input, Clock, VCC, , , , );


--q[12] is q[12]
--operation mode is normal

q[12]_lut_out = A1L08 # q[12] & A1L18 & !Reset;
q[12] = DFFEA(q[12]_lut_out, Clock, VCC, , , , );


--q[11] is q[11]
--operation mode is normal

q[11]_lut_out = A1L38 # A1L97 & A1L28 & !Count[2];
q[11] = DFFEA(q[11]_lut_out, Clock, VCC, , , , );


--q[10] is q[10]
--operation mode is normal

q[10]_lut_out = A1L48 # A1L1 & A1L97 & !Count[2];
q[10] = DFFEA(q[10]_lut_out, Clock, VCC, , , , );


--q[9] is q[9]
--operation mode is normal

q[9]_lut_out = A1L58 # q[9] & A1L68 & !Reset;
q[9] = DFFEA(q[9]_lut_out, Clock, VCC, , , , );


--q[8] is q[8]
--operation mode is normal

q[8]_lut_out = A1L78 # q[8] & A1L88 & !Reset;
q[8] = DFFEA(q[8]_lut_out, Clock, VCC, , , , );


--q[7] is q[7]
--operation mode is normal

q[7]_lut_out = A1L98 # A1L97 & A1L25 & !Count[0];
q[7] = DFFEA(q[7]_lut_out, Clock, VCC, , , , );


--q[6] is q[6]
--operation mode is normal

q[6]_lut_out = A1L34 & (A1L45 # Strait_A) # !A1L34 & A1L45 & !Strait_A;
q[6]_sload_eqn = (A1L15 & q[6]) # (!A1L15 & q[6]_lut_out);
q[6]_reg_input = q[6]_sload_eqn & !Reset;
q[6] = DFFEA(q[6]_reg_input, Clock, VCC, , , , );


--A1L311 is Road_sign~0
--operation mode is normal

A1L311 = !q[6] & (Clock_4Hz # Blink);


--q[5] is q[5]
--operation mode is normal

q[5]_lut_out = A1L65 & (A1L75 # !Strait_A) # !A1L65 & A1L75 & Strait_A;
q[5]_sload_eqn = (A1L15 & q[5]) # (!A1L15 & q[5]_lut_out);
q[5]_reg_input = q[5]_sload_eqn & !Reset;
q[5] = DFFEA(q[5]_reg_input, Clock, VCC, , , , );


--A1L411 is Road_sign~1
--operation mode is normal

A1L411 = !q[5] & (Clock_4Hz # Blink);


--q[4] is q[4]
--operation mode is normal

q[4]_lut_out = A1L44 & (A1L84 # Strait_A) # !A1L44 & A1L84 & !Strait_A;
q[4]_sload_eqn = (A1L15 & q[4]) # (!A1L15 & q[4]_lut_out);
q[4]_reg_input = q[4]_sload_eqn & !Reset;
q[4] = DFFEA(q[4]_reg_input, Clock, VCC, , , , );


--A1L511 is Road_sign~2
--operation mode is normal

A1L511 = !q[4] & (Clock_4Hz # Blink);


--q[3] is q[3]
--operation mode is normal

q[3]_lut_out = A1L19 # A1L29 & !A1L15 & !Reset;
q[3] = DFFEA(q[3]_lut_out, Clock, VCC, , , , );


--A1L611 is Road_sign~3
--operation mode is normal

A1L611 = !q[3] & (Clock_4Hz # Blink);


--q[2] is q[2]
--operation mode is normal

q[2]_lut_out = A1L54 & (A1L95 # Strait_A) # !A1L54 & A1L95 & !Strait_A;
q[2]_sload_eqn = (A1L15 & q[2]) # (!A1L15 & q[2]_lut_out);
q[2]_reg_input = q[2]_sload_eqn & !Reset;
q[2] = DFFEA(q[2]_reg_input, Clock, VCC, , , , );


--A1L711 is Road_sign~4
--operation mode is normal

A1L711 = !q[2] & (Clock_4Hz # Blink);


--q[1] is q[1]
--operation mode is normal

q[1]_lut_out = A1L64 & (A1L16 # Strait_A) # !A1L64 & A1L16 & !Strait_A;
q[1]_sload_eqn = (A1L15 & q[1]) # (!A1L15 & q[1]_lut_out);
q[1]_reg_input = q[1]_sload_eqn & !Reset;
q[1] = DFFEA(q[1]_reg_input, Clock, VCC, , , , );


--A1L811 is Road_sign~5
--operation mode is normal

A1L811 = !q[1] & (Clock_4Hz # Blink);


--q[0] is q[0]
--operation mode is normal

q[0]_lut_out = A1L74 & (A1L36 # Strait_A) # !A1L74 & A1L36 & !Strait_A;
q[0]_sload_eqn = (A1L15 & q[0]) # (!A1L15 & q[0]_lut_out);
q[0]_reg_input = q[0]_sload_eqn & !Reset;
q[0] = DFFEA(q[0]_reg_input, Clock, VCC, , , , );


--A1L911 is Road_sign~6
--operation mode is normal

A1L911 = !q[0] & (Clock_4Hz # Blink);


--State[0] is State[0]
--operation mode is normal

State[0]_lut_out = !Reset & (State[0] $ !A1L59);
State[0] = DFFEA(State[0]_lut_out, Clock_1Hz, VCC, , , , );


--State[1] is State[1]
--operation mode is normal

State[1]_lut_out = !Reset & (State[1] $ (!A1L59 & State[0]));
State[1] = DFFEA(State[1]_lut_out, Clock_1Hz, VCC, , , , );


--Clock_1Hz is Clock_1Hz
--operation mode is normal

Clock_1Hz_lut_out = !Clock_1Hz;
Clock_1Hz = DFFEA(Clock_1Hz_lut_out, Clock_4Hz, VCC, , A1L49, , );


--C1_safe_q[4] is lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[4]
--operation mode is normal

C1_safe_q[4]_carry_eqn = C1L8;
C1_safe_q[4]_lut_out = C1_safe_q[4] $ !C1_safe_q[4]_carry_eqn;
C1_safe_q[4] = DFFEA(C1_safe_q[4]_lut_out, Clock, VCC, , , , );


--C1_safe_q[2] is lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[2]
--operation mode is arithmetic

C1_safe_q[2]_carry_eqn = C1L4;
C1_safe_q[2]_lut_out = C1_safe_q[2] $ !C1_safe_q[2]_carry_eqn;
C1_safe_q[2] = DFFEA(C1_safe_q[2]_lut_out, Clock, VCC, , , , );

--C1L6 is lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

C1L6 = CARRY(!C1_safe_q[2] & !C1L4);


--C1_safe_q[3] is lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[3]
--operation mode is arithmetic

C1_safe_q[3]_carry_eqn = C1L6;
C1_safe_q[3]_lut_out = C1_safe_q[3] $ C1_safe_q[3]_carry_eqn;
C1_safe_q[3] = DFFEA(C1_safe_q[3]_lut_out, Clock, VCC, , , , );

--C1L8 is lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|counter_cella3~COUT
--operation mode is arithmetic

C1L8 = CARRY(C1_safe_q[3] # !C1L6);


--C1_safe_q[0] is lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[0]
--operation mode is arithmetic

C1_safe_q[0]_lut_out = !C1_safe_q[0];
C1_safe_q[0] = DFFEA(C1_safe_q[0]_lut_out, Clock, VCC, , , , );

--C1L2 is lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

C1L2 = CARRY(!C1_safe_q[0]);


--C1_safe_q[1] is lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[1]
--operation mode is arithmetic

C1_safe_q[1]_carry_eqn = C1L2;
C1_safe_q[1]_lut_out = C1_safe_q[1] $ C1_safe_q[1]_carry_eqn;
C1_safe_q[1] = DFFEA(C1_safe_q[1]_lut_out, Clock, VCC, , , , );

--C1L4 is lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

C1L4 = CARRY(C1_safe_q[1] # !C1L2);


--A1L69 is reduce_nor~36
--operation mode is normal

A1L69 = C1_safe_q[0] # C1_safe_q[1];


--A1L39 is reduce_nor~0
--operation mode is normal

A1L39 = !C1_safe_q[4] & !C1_safe_q[2] & !C1_safe_q[3] & !A1L69;


--Count_Down[2] is Count_Down[2]
--operation mode is normal

Count_Down[2]_lut_out = !Reset & (Count_Down[2] $ (!Count_Down[1] & !Count_Down[0]));
Count_Down[2] = DFFEA(Count_Down[2]_lut_out, Clock_1Hz, VCC, , , , );


--Count_Down[1] is Count_Down[1]
--operation mode is normal

Count_Down[1]_lut_out = !Reset & (Count_Down[1] $ !Count_Down[0]);
Count_Down[1] = DFFEA(Count_Down[1]_lut_out, Clock_1Hz, VCC, , , , );


--Count_Down[0] is Count_Down[0]
--operation mode is normal

Count_Down[0]_lut_out = !Reset & !Count_Down[0];
Count_Down[0] = DFFEA(Count_Down[0]_lut_out, Clock_1Hz, VCC, , , , );


--Count[1] is Count[1]
--operation mode is normal

Count[1]_lut_out = !Count[1];
Count[1] = DFFEA(Count[1]_lut_out, Clock, VCC, , A1L51, , );


--Count[0] is Count[0]
--operation mode is normal

Count[0]_lut_out = !Count[0];
Count[0] = DFFEA(Count[0]_lut_out, Clock, VCC, , !Reset, , );


--A1L14 is Mux~219
--operation mode is normal

A1L14 = Count[1] # Count[0];


--A1L24 is Mux~374
--operation mode is normal

A1L24 = q[13] & Count[1] & Count[0];


--Count[2] is Count[2]
--operation mode is normal

Count[2]_lut_out = !Count[2];