traffic.tan.rpt
来自「利用vhdl编写的模拟交通灯的程序」· RPT 代码 · 共 330 行 · 第 1/5 页
RPT
330 行
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count[0] ; q[12] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[1] ; Count_Down_LCD[4]~reg0 ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[1] ; Count_Down_LCD[1]~reg0 ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[1] ; Count_Down_LCD[5]~reg0 ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[1] ; Count_Down_LCD[3]~reg0 ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[1] ; Count_Down_LCD[2]~reg0 ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[1] ; Count_Down_LCD[0]~reg0 ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[1] ; Count_Down_LCD[6]~reg0 ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count[1] ; q[3] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count[2] ; q[13] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[0] ; Clock_4Hz ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count[1] ; q[9] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count[1] ; q[12] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[4] ; Clock_4Hz ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count[2] ; q[10] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count[1] ; q[2] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[3] ; Clock_4Hz ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_1Hz[0] ; Clock_1Hz ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count[0] ; Count[1] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[2] ; Blink ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[2] ; Clock_4Hz ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[0] ; Count_Down[1] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count[1] ; q[8] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_1Hz[1] ; Clock_1Hz ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[1] ; Blink ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; q[1] ; q[1] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; q[0] ; q[0] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[1] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[4] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[2] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[4] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[1] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[3] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[0] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[4] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; q[13] ; q[13] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[2] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[3] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[1] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[2] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[0] ; Turn_A ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[0] ; Strait_A ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[0] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[3] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; q[2] ; q[2] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[0] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[2] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[0] ; Block_A ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[1] ; Turn_A ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[1] ; Strait_A ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count[0] ; q[7] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[1] ; Count_Down[2] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[0] ; Count_Down[2] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[3] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[4] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[0] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[1] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; q[7] ; q[7] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; q[10] ; q[10] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[0] ; Blink ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; q[3] ; q[3] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; q[11] ; q[11] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[0] ; State[1] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[0] ; State[0] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[2] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[2] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[4] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[4] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[1] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[1] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_Down[2] ; Count_Down[2] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[1] ; Turn_B ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[1] ; Strait_B ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; Count_1Hz[0] ; Count_1Hz[1] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; State[1] ; State[1] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[3] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[3] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[0] ; lpm_counter:Count_4Hz_rtl_0|cntr_037:auto_generated|safe_q[0] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; q[9] ; q[9] ; Clock ; Clock ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; q[12] ; q[12] ; Clock ; Clock ; None ; None ; None ;
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