shopping.tan.rpt

利用vhdl编写的商店的模型程序

; Run Minimum Analysis                                  ; Off                ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                               ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------+-----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                                     ; To        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------+-----------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 9.734 ns                         ; coin1                                                    ; ram[0][4] ;            ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 13.162 ns                        ; lpm_counter:quan_rtl_0|cntr_om8:auto_generated|safe_q[0] ; Seg7[4]   ; clk        ;          ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; 160.72 MHz ( period = 6.222 ns ) ; lpm_counter:quan_rtl_0|cntr_om8:auto_generated|safe_q[1] ; ram[0][4] ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                          ;           ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+----------------------------------------------------------+-----------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                     ; To                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------+----------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 160.72 MHz ( period = 6.222 ns )                    ; lpm_counter:quan_rtl_0|cntr_om8:auto_generated|safe_q[1] ; ram[0][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 163.19 MHz ( period = 6.128 ns )                    ; pri[0]                                                   ; ram[0][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 165.43 MHz ( period = 6.045 ns )                    ; lpm_counter:quan_rtl_0|cntr_om8:auto_generated|safe_q[2] ; ram[0][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 167.22 MHz ( period = 5.980 ns )                    ; coin[0]                                                  ; ram[0][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 167.79 MHz ( period = 5.960 ns )                    ; lpm_counter:quan_rtl_0|cntr_om8:auto_generated|safe_q[1] ; ram[1][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 168.29 MHz ( period = 5.942 ns )                    ; lpm_counter:quan_rtl_0|cntr_om8:auto_generated|safe_q[1] ; ram[3][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 168.41 MHz ( period = 5.938 ns )                    ; lpm_counter:quan_rtl_0|cntr_om8:auto_generated|safe_q[3] ; ram[0][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 169.32 MHz ( period = 5.906 ns )                    ; pri[1]                                                   ; ram[0][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 170.36 MHz ( period = 5.870 ns )                    ; pri[2]                                                   ; ram[0][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 170.36 MHz ( period = 5.870 ns )                    ; lpm_counter:quan_rtl_0|cntr_om8:auto_generated|safe_q[1] ; ram[2][7]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 170.47 MHz ( period = 5.866 ns )                    ; pri[0]                                                   ; ram[1][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 171.00 MHz ( period = 5.848 ns )                    ; pri[0]                                                   ; ram[3][4]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 171.32 MHz ( period = 5.837 ns )                    ; lpm_counter:quan_rtl_0|cntr_om8:auto_generated|safe_q[1] ; ram[2][5]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;
; N/A                                     ; 171.32 MHz ( period = 5.837 ns )                    ; lpm_counter:quan_rtl_0|cntr_om8:auto_generated|safe_q[1] ; ram[2][1]                                                ; clk        ; clk      ; None                        ; None                      ; None                    ;