shopping.fit.qmsg

利用vhdl编写的商店的模型程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 06 14:34:31 2006 " "Info: Processing started: Tue Jun 06 14:34:31 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off shopping -c shopping " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off shopping -c shopping" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "shopping EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design shopping" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation -- maximum Fitter effort will be used to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 152 " "Info: Automatically promoted signal clk to use Global clock in PIN 152" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "set Global clock " "Info: Automatically promoted some destinations of signal set to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "act10~reg0 " "Info: Destination act10~reg0 may be non-global or may not use global clock" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 40 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "act5~reg0 " "Info: Destination act5~reg0 may be non-global or may not use global clock" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 40 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "item\[1\]~50 " "Info: Destination item\[1\]~50 may be non-global or may not use global clock" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 40 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "coin\[3\] " "Info: Destination coin\[3\] may be non-global or may not use global clock" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 40 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "coin\[2\] " "Info: Destination coin\[2\] may be non-global or may not use global clock" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 40 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "coin\[1\] " "Info: Destination coin\[1\] may be non-global or may not use global clock" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 40 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "coin\[0\] " "Info: Destination coin\[0\] may be non-global or may not use global clock" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 40 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "quan\[3\]~248 " "Info: Destination quan\[3\]~248 may be non-global or may not use global clock" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 40 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "pri\[3\]~5 " "Info: Destination pri\[3\]~5 may be non-global or may not use global clock" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 40 -1 0 } }  } 0}  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "set " "Info: Pin set drives global clock, but is not placed in a dedicated clock pin position" {  } { { "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" "" "" { Text "I:/共享/310exp_BY_Dong/18 shopping/shopping.vhd" 8 -1 0 } } { "g:/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus41/bin/Assignment Editor.qase" 1 { { 0 "set" } } } } { "I:/共享/310exp_BY_Dong/18 shopping/db/shopping_cmp.qrpt" "" "" { Report "I:/共享/310exp_BY_Dong/18 shopping/db/shopping_cmp.qrpt" Compiler "shopping" "UNKNOWN" "V1" "I:/共享/310exp_BY_Dong/18 shopping/db/shopping.quartus_db" { Floorplan "" "" "" { set } "NODE_NAME" } } } { "I:/共享/310exp_BY_Dong/18 shopping/shopping.fld" "" "" { Floorplan "I:/共享/310exp_BY_Dong/18 shopping/shopping.fld" "" "" { set } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}