shopping.map.rpt

利用vhdl编写的商店的模型程序

; Number of WYSIWYG registers                            ; 18    ;
; Number of synthesis-generated registers                ; 44    ;
; Number of cells with combinational logic only          ; 130   ;
; Number of cells with registers only                    ; 34    ;
; Number of cells with combinational logic and registers ; 28    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 8     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 32    ;
; Number of registers using Clock Enable       ; 52    ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
shopping
 |-- lpm_counter:quan_rtl_0
      |-- cntr_om8:auto_generated
 |-- lpm_counter:t_rtl_1
      |-- cntr_pt6:auto_generated


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                 ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------+
; Compilation Hierarchy Node      ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                      ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------+
; |shopping                       ; 192 (178)   ; 62           ; 0           ; 41   ; 0            ; 130 (130)    ; 34 (34)           ; 28 (14)          ; 18 (4)          ; |shopping                                                ;
;    |lpm_counter:quan_rtl_0|     ; 4 (0)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; |shopping|lpm_counter:quan_rtl_0                         ;
;       |cntr_om8:auto_generated| ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; |shopping|lpm_counter:quan_rtl_0|cntr_om8:auto_generated ;
;    |lpm_counter:t_rtl_1|        ; 10 (0)      ; 10           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 10 (0)           ; 10 (0)          ; |shopping|lpm_counter:t_rtl_1                            ;
;       |cntr_pt6:auto_generated| ; 10 (10)     ; 10           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 10 (10)          ; 10 (10)         ; |shopping|lpm_counter:t_rtl_1|cntr_pt6:auto_generated    ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in I:/共享/310exp_BY_Dong/18 shopping/shopping.map.eqn.


+-------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                  ;
+-------------------------------------------------------+-----------------+
; File Name                                             ; Used in Netlist ;
+-------------------------------------------------------+-----------------+
; shopping.vhd                                          ; yes             ;
; g:/quartus41/libraries/megafunctions/lpm_counter.tdf  ; yes             ;
; g:/quartus41/libraries/megafunctions/lpm_constant.inc ; yes             ;
; I:/共享/310exp_BY_Dong/18 shopping/db/cntr_om8.tdf    ; yes             ;
; I:/共享/310exp_BY_Dong/18 shopping/db/cntr_pt6.tdf    ; yes             ;
+-------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 192     ;
; Total combinational functions     ; 158     ;
; Total 4-input functions           ; 112     ;
; Total 3-input functions           ; 19      ;
; Total 2-input functions           ; 13      ;
; Total 1-input functions           ; 14      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 62      ;
; Total logic cells in carry chains ; 18      ;
; I/O pins                          ; 41      ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 62      ;
; Total fan-out                     ; 812     ;
; Average fan-out                   ; 3.48    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Jun 06 14:34:24 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off shopping -c shopping
Info: Found 2 design units, including 1 entities, in source file shopping.vhd
    Info: Found design unit 1: shopping-behav
    Info: Found entity 1: shopping
Warning: VHDL Process Statement warning at shopping.vhd(41): signal price is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at shopping.vhd(41): signal quantity is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at shopping.vhd(41): signal item is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at shopping.vhd(152): signal y0 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at shopping.vhd(154): signal y1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at shopping.vhd(156): signal y2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at shopping.vhd(143): signal or variable segslt may not be assigned a new value in every possible path through the Process Statement. Signal or variable segslt holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at shopping.vhd(143): signal or variable seg7 may not be assigned a new value in every possible path through the Process Statement. Signal or variable seg7 holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Ignored 11 buffer(s)
    Info: Ignored 11 SOFT buffer(s)
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: quan[0]~252
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=10) from the following logic: t[0]~0
Info: Found 1 design units, including 1 entities, in source file g:/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_om8.tdf
    Info: Found entity 1: cntr_om8
Info: Found 1 design units, including 1 entities, in source file db/cntr_pt6.tdf
    Info: Found entity 1: cntr_pt6
Warning: Output pins are stuck at VCC or GND
    Warning: Pin Seg7[0] stuck at GND
    Warning: Pin Segslt[7] stuck at GND
    Warning: Pin Segslt[6] stuck at GND
    Warning: Pin Segslt[5] stuck at GND
    Warning: Pin Segslt[4] stuck at GND
    Warning: Pin Segslt[3] stuck at GND
Info: Implemented 233 device resources after synthesis - the final resource count might be different
    Info: Implemented 15 input pins
    Info: Implemented 26 output pins
    Info: Implemented 192 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings
    Info: Processing ended: Tue Jun 06 14:34:29 2006
    Info: Elapsed time: 00:00:05