snake.v

利用VHDL语言编写的一个蛇形的程序

module Snake(CLK, RST, SCAN, SEG7);
	input CLK, RST;         //复位按键低有效,输入时钟20MHz
	output[1:8] SCAN;       //数码管选择信号
	output[1:8] SEG7;       //数码管显示信号
	
	reg[1:8] SCAN, SEG7,q;
	reg[23:0] count;
	reg clk_2HZ;
	reg sign;               //蛇行方向       
	
	reg[31:0] snak;			//蛇行状态
	reg[4:0] loop;          //每圈状态
	reg[1:0] loopn;         //行进圈数
	reg[2:0] scnt;
	
	always@(posedge CLK)begin            //分频模块产生2Hz时钟
		if (count==9999999)begin
			count<=0;
			clk_2HZ<=1;
		end else begin
			count<=count+1;
			clk_2HZ<=0;
		end
	end
	
	always@(posedge clk_2HZ)begin
		if (RST==0) begin
			loop<=0;
			loopn<=0;
			sign<=0;
			snak<=0;
			q<=0;
		end else begin
			if (sign==0)begin                 //正转
				if (loop==19)begin
					if (loopn==3)begin
						loopn<=0;
						sign<=~sign;
					end else 
						loopn<=loopn+1;
					loop<=0;
				end else begin
					loop<=loop+1;
				end
				
				case (loopn)
					0: q <={8'B0110_000,sign};
					1: q <={8'B1101_101,sign};
					2: q <={8'B1111_001,sign};
					default: q <={8'B0110_011,sign};
				endcase
				case (loop)                //正转状态
					5'B00000: snak<=32'B10000000100000001000000000000000;
					5'B00001: snak<=32'B00000000100000001000000010000000;
					5'B00010: snak<=32'B00000000000000001000000011000000;
					5'B00011: snak<=32'B00000000000000000000000011000010;
					5'B00100: snak<=32'B00000000000000000000001001000010;
					5'B00101: snak<=32'B00000000000000100000001000000010;
					5'B00110: snak<=32'B00000010000000100000001000000000;
					5'B00111: snak<=32'B00001010000000100000000000000000;
					5'B01000: snak<=32'B00011010000000000000000000000000;
					5'B01001: snak<=32'B00011000000100000000000000000000;
					5'B01010: snak<=32'B00010000000100000001000000000000;
					5'B01011: snak<=32'B00000000000100000001000000010000;
					5'B01100: snak<=32'B00000000000000000001000000110000;
					5'B01101: snak<=32'B00000000000000000000000000110010;
					5'B01110: snak<=32'B00000000000000000000001000100010;
					5'B01111: snak<=32'B00000000000000100000001000000010;
					5'B10000: snak<=32'B00000010000000100000001000000000;
					5'B10001: snak<=32'B00000110000000100000000000000000;
					5'B10010: snak<=32'B10000110000000000000000000000000;
					5'B10011: snak<=32'B10000100100000000000000000000000;
					default:  snak<=32'B00000000000000000000000000000000;
				endcase
			end else begin                 //反转
				if (loop==19)begin
					if (loopn==3)begin
						loopn<=0;
						sign<=~sign;
					end else 
						loopn<=loopn+1;
					loop<=0;
				end else begin
					loop<=loop+1;
				end
				case (loopn)
					0: q <={8'B0110_000,sign};
					1: q <=8'B1101_1010;
					2: q <=8'B1111_0010;
					default: q <=8'B0110_0110;
				endcase
				case (loop)                //反转状态
					5'B00000: snak<=32'B10000000100000001000000000000000;
					5'B00001: snak<=32'B10000100100000000000000000000000;
					5'B00010: snak<=32'B10000110000000000000000000000000;
					5'B00011: snak<=32'B00000110000000100000000000000000;
					5'B00100: snak<=32'B00000010000000100000001000000000;
					5'B00101: snak<=32'B00000000000000100000001000000010;
					5'B00110: snak<=32'B00000000000000000000001000100010;
					5'B00111: snak<=32'B00000000000000000000000000110010;
					5'B01000: snak<=32'B00000000000000000001000000110000;
					5'B01001: snak<=32'B00000000000100000001000000010000;
					5'B01010: snak<=32'B00010000000100000001000000000000;
					5'B01011: snak<=32'B00011000000100000000000000000000;
					5'B01100: snak<=32'B00011010000000000000000000000000;
					5'B01101: snak<=32'B00001010000000100000000000000000;
					5'B01110: snak<=32'B00000010000000100000001000000000;
					5'B01111: snak<=32'B00000000000000100000001000000010;
					5'B10000: snak<=32'B00000000000000000000001001000010;
					5'B10001: snak<=32'B00000000000000000000000011000010;
					5'B10010: snak<=32'B00000000000000001000000011000000;
					5'B10011: snak<=32'B00000000100000001000000010000000;
					default:  snak<=32'B00000000000000000000000000000000;
				endcase
			end
		end
	end
	
	always@(posedge count[8])begin
		if (scnt==3'B101)
			scnt<=0;
		else scnt<=scnt+1;
		case (scnt)
			3'B001: begin SEG7<=snak[31:24];SCAN<=8'B10000000; end
			3'B010: begin SEG7<=snak[23:16];SCAN<=8'B01000000; end
			3'B011: begin SEG7<=snak[15:8];SCAN<=8'B00100000; end
			3'B100: begin SEG7<=snak[7:0];SCAN<=8'B00010000; end
			3'B101: begin SEG7<=q;SCAN<=8'B00001000; end
			default: SEG7<=8'B0000_0000;
		endcase
	end
endmodule