snake.fit.qmsg

利用VHDL语言编写的一个蛇形的程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 06 11:20:27 2006 " "Info: Processing started: Tue Jun 06 11:20:27 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off Snake -c Snake " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off Snake -c Snake" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "Snake EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design Snake" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation -- maximum Fitter effort will be used to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN 28 " "Info: Automatically promoted signal CLK to use Global clock in PIN 28" {  } { { "I:/共享/310exp_BY_Dong/02 snake/Snake.v" "" "" { Text "I:/共享/310exp_BY_Dong/02 snake/Snake.v" 2 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk_2HZ Global clock " "Info: Automatically promoted signal clk_2HZ to use Global clock" {  } { { "I:/共享/310exp_BY_Dong/02 snake/Snake.v" "" "" { Text "I:/共享/310exp_BY_Dong/02 snake/Snake.v" 24 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "count\[8\] Global clock " "Info: Automatically promoted some destinations of signal count\[8\] to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "add~37 " "Info: Destination add~37 may be non-global or may not use global clock" {  } {  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reduce_nor~211 " "Info: Destination reduce_nor~211 may be non-global or may not use global clock" {  } {  } 0}  } { { "I:/共享/310exp_BY_Dong/02 snake/Snake.v" "" "" { Text "I:/共享/310exp_BY_Dong/02 snake/Snake.v" 24 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.946 ns register register " "Info: Estimated most critical path is register to register delay of 3.946 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[17\] 1 REG LAB_X7_Y13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y13; Fanout = 4; REG Node = 'count\[17\]'" {  } { { "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" "" "" { Report "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" Compiler "Snake" "UNKNOWN" "V1" "I:/共享/310exp_BY_Dong/02 snake/db/Snake.quartus_db" { Floorplan "" "" "" { count[17] } "NODE_NAME" } } } { "I:/共享/310exp_BY_Dong/02 snake/Snake.v" "" "" { Text "I:/共享/310exp_BY_Dong/02 snake/Snake.v" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.496 ns) + CELL(0.442 ns) 0.938 ns reduce_nor~212 2 COMB LAB_X6_Y13 1 " "Info: 2: + IC(0.496 ns) + CELL(0.442 ns) = 0.938 ns; Loc. = LAB_X6_Y13; Fanout = 1; COMB Node = 'reduce_nor~212'" {  } { { "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" "" "" { Report "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" Compiler "Snake" "UNKNOWN" "V1" "I:/共享/310exp_BY_Dong/02 snake/db/Snake.quartus_db" { Floorplan "" "" "0.938 ns" { count[17] reduce_nor~212 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(0.442 ns) 2.186 ns reduce_nor~215 3 COMB LAB_X6_Y14 9 " "Info: 3: + IC(0.806 ns) + CELL(0.442 ns) = 2.186 ns; Loc. = LAB_X6_Y14; Fanout = 9; COMB Node = 'reduce_nor~215'" {  } { { "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" "" "" { Report "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" Compiler "Snake" "UNKNOWN" "V1" "I:/共享/310exp_BY_Dong/02 snake/db/Snake.quartus_db" { Floorplan "" "" "1.248 ns" { reduce_nor~212 reduce_nor~215 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.738 ns) 3.946 ns clk_2HZ 4 REG LAB_X8_Y10 31 " "Info: 4: + IC(1.022 ns) + CELL(0.738 ns) = 3.946 ns; Loc. = LAB_X8_Y10; Fanout = 31; REG Node = 'clk_2HZ'" {  } { { "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" "" "" { Report "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" Compiler "Snake" "UNKNOWN" "V1" "I:/共享/310exp_BY_Dong/02 snake/db/Snake.quartus_db" { Floorplan "" "" "1.760 ns" { reduce_nor~215 clk_2HZ } "NODE_NAME" } } } { "I:/共享/310exp_BY_Dong/02 snake/Snake.v" "" "" { Text "I:/共享/310exp_BY_Dong/02 snake/Snake.v" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 41.10 % " "Info: Total cell delay = 1.622 ns ( 41.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.324 ns 58.90 % " "Info: Total interconnect delay = 2.324 ns ( 58.90 % )" {  } {  } 0}  } { { "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" "" "" { Report "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" Compiler "Snake" "UNKNOWN" "V1" "I:/共享/310exp_BY_Dong/02 snake/db/Snake.quartus_db" { Floorplan "" "" "3.946 ns" { count[17] reduce_nor~212 reduce_nor~215 clk_2HZ } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "1 " "Info: Fitter placement operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "1 " "Info: Fitter routing operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SCAN\[6\] GND " "Info: Pin SCAN\[6\] has GND driving its datain port" {  } { { "I:/共享/310exp_BY_Dong/02 snake/Snake.v" "" "" { Text "I:/共享/310exp_BY_Dong/02 snake/Snake.v" 3 -1 0 } } { "g:/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SCAN\[6\]" } } } } { "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" "" "" { Report "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" Compiler "Snake" "UNKNOWN" "V1" "I:/共享/310exp_BY_Dong/02 snake/db/Snake.quartus_db" { Floorplan "" "" "" { SCAN[6] } "NODE_NAME" } } } { "I:/共享/310exp_BY_Dong/02 snake/Snake.fld" "" "" { Floorplan "I:/共享/310exp_BY_Dong/02 snake/Snake.fld" "" "" { SCAN[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SCAN\[7\] GND " "Info: Pin SCAN\[7\] has GND driving its datain port" {  } { { "I:/共享/310exp_BY_Dong/02 snake/Snake.v" "" "" { Text "I:/共享/310exp_BY_Dong/02 snake/Snake.v" 3 -1 0 } } { "g:/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SCAN\[7\]" } } } } { "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" "" "" { Report "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" Compiler "Snake" "UNKNOWN" "V1" "I:/共享/310exp_BY_Dong/02 snake/db/Snake.quartus_db" { Floorplan "" "" "" { SCAN[7] } "NODE_NAME" } } } { "I:/共享/310exp_BY_Dong/02 snake/Snake.fld" "" "" { Floorplan "I:/共享/310exp_BY_Dong/02 snake/Snake.fld" "" "" { SCAN[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SCAN\[8\] GND " "Info: Pin SCAN\[8\] has GND driving its datain port" {  } { { "I:/共享/310exp_BY_Dong/02 snake/Snake.v" "" "" { Text "I:/共享/310exp_BY_Dong/02 snake/Snake.v" 3 -1 0 } } { "g:/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus41/bin/Assignment Editor.qase" 1 { { 0 "SCAN\[8\]" } } } } { "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" "" "" { Report "I:/共享/310exp_BY_Dong/02 snake/db/Snake_cmp.qrpt" Compiler "Snake" "UNKNOWN" "V1" "I:/共享/310exp_BY_Dong/02 snake/db/Snake.quartus_db" { Floorplan "" "" "" { SCAN[8] } "NODE_NAME" } } } { "I:/共享/310exp_BY_Dong/02 snake/Snake.fld" "" "" { Floorplan "I:/共享/310exp_BY_Dong/02 snake/Snake.fld" "" "" { SCAN[8] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 06 11:20:36 2006 " "Info: Processing ended: Tue Jun 06 11:20:36 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}