fenpin.vhd

来自「利用VHDL语言编写的一个蛇形的程序」· VHDL 代码 · 共 27 行

library ieee;                                 
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk:in std_logic;
     p  :out std_logic;
q  :out std_logic);
end;
architecture fenpin of fenpin is
signal count:std_logic_vector(15 downto 0);
signal q1:std_logic;
begin
process(clk)
begin
if(clk'event and clk='1')then
      if(count="100110001001011001111111")then   -----20MHz时钟分频为2Hz时钟
            count<=(others=>'0');
            q1<='1';
      else count<=count+1;
            q1<='0';
      end if;
end if;
end process;
q<=q1;
p<=count(8);
end;