📄 music.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk5MHz " "Info: Assuming node \"clk5MHz\" is an undefined clock" { } { { "music_1.bdf" "" { Schematic "E:/design/junior/music_1/music_1.bdf" { { 0 352 520 16 "clk5MHz" "" } } } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "clk5MHz" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1kHz " "Info: Assuming node \"clk1kHz\" is an undefined clock" { } { { "music_1.bdf" "" { Schematic "E:/design/junior/music_1/music_1.bdf" { { 72 -48 120 88 "clk1kHz" "" } } } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "clk1kHz" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "speaker:inst3\|preclk " "Info: Detected ripple clock \"speaker:inst3\|preclk\" as buffer" { } { { "speaker.vhd" "" { Text "E:/design/junior/music_1/speaker.vhd" 12 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "speaker:inst3\|preclk" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "music_rom:inst1\|clk_4hz " "Info: Detected ripple clock \"music_rom:inst1\|clk_4hz\" as buffer" { } { { "music_rom.vhd" "" { Text "E:/design/junior/music_1/music_rom.vhd" 14 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "music_rom:inst1\|clk_4hz" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "speaker:inst3\|fullspks " "Info: Detected ripple clock \"speaker:inst3\|fullspks\" as buffer" { } { { "speaker.vhd" "" { Text "E:/design/junior/music_1/speaker.vhd" 13 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "speaker:inst3\|fullspks" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk5MHz register speaker:inst3\|\\genspks:count11\[3\] register speaker:inst3\|\\genspks:count11\[4\] 203.58 MHz 4.912 ns Internal " "Info: Clock \"clk5MHz\" has Internal fmax of 203.58 MHz between source register \"speaker:inst3\|\\genspks:count11\[3\]\" and destination register \"speaker:inst3\|\\genspks:count11\[4\]\" (period= 4.912 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.651 ns + Longest register register " "Info: + Longest register to register delay is 4.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns speaker:inst3\|\\genspks:count11\[3\] 1 REG LC_X20_Y6_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y6_N8; Fanout = 4; REG Node = 'speaker:inst3\|\\genspks:count11\[3\]'" { } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { speaker:inst3|\genspks:count11[3] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.291 ns) + CELL(0.590 ns) 1.881 ns speaker:inst3\|Equal1~98 2 COMB LC_X20_Y5_N6 2 " "Info: 2: + IC(1.291 ns) + CELL(0.590 ns) = 1.881 ns; Loc. = LC_X20_Y5_N6; Fanout = 2; COMB Node = 'speaker:inst3\|Equal1~98'" { } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.881 ns" { speaker:inst3|\genspks:count11[3] speaker:inst3|Equal1~98 } "NODE_NAME" } } { "speaker.vhd" "" { Text "E:/design/junior/music_1/speaker.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.177 ns speaker:inst3\|Equal1~101 3 COMB LC_X20_Y5_N7 11 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.177 ns; Loc. = LC_X20_Y5_N7; Fanout = 11; COMB Node = 'speaker:inst3\|Equal1~101'" { } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "0.296 ns" { speaker:inst3|Equal1~98 speaker:inst3|Equal1~101 } "NODE_NAME" } } { "speaker.vhd" "" { Text "E:/design/junior/music_1/speaker.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.249 ns) + CELL(1.225 ns) 4.651 ns speaker:inst3\|\\genspks:count11\[4\] 4 REG LC_X20_Y6_N9 3 " "Info: 4: + IC(1.249 ns) + CELL(1.225 ns) = 4.651 ns; Loc. = LC_X20_Y6_N9; Fanout = 3; REG Node = 'speaker:inst3\|\\genspks:count11\[4\]'" { } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.474 ns" { speaker:inst3|Equal1~101 speaker:inst3|\genspks:count11[4] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.929 ns ( 41.47 % ) " "Info: Total cell delay = 1.929 ns ( 41.47 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.722 ns ( 58.53 % ) " "Info: Total interconnect delay = 2.722 ns ( 58.53 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.651 ns" { speaker:inst3|\genspks:count11[3] speaker:inst3|Equal1~98 speaker:inst3|Equal1~101 speaker:inst3|\genspks:count11[4] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "4.651 ns" { speaker:inst3|\genspks:count11[3] speaker:inst3|Equal1~98 speaker:inst3|Equal1~101 speaker:inst3|\genspks:count11[4] } { 0.000ns 1.291ns 0.182ns 1.249ns } { 0.000ns 0.590ns 0.114ns 1.225ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk5MHz destination 7.423 ns + Shortest register " "Info: + Shortest clock path from clock \"clk5MHz\" to destination register is 7.423 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk5MHz 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk5MHz'" { } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { clk5MHz } "NODE_NAME" } } { "music_1.bdf" "" { Schematic "E:/design/junior/music_1/music_1.bdf" { { 0 352 520 16 "clk5MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns speaker:inst3\|preclk 2 REG LC_X26_Y6_N5 12 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X26_Y6_N5; Fanout = 12; REG Node = 'speaker:inst3\|preclk'" { } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.537 ns" { clk5MHz speaker:inst3|preclk } "NODE_NAME" } } { "speaker.vhd" "" { Text "E:/design/junior/music_1/speaker.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.706 ns) + CELL(0.711 ns) 7.423 ns speaker:inst3\|\\genspks:count11\[4\] 3 REG LC_X20_Y6_N9 3 " "Info: 3: + IC(3.706 ns) + CELL(0.711 ns) = 7.423 ns; Loc. = LC_X20_Y6_N9; Fanout = 3; REG Node = 'speaker:inst3\|\\genspks:count11\[4\]'" { } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.417 ns" { speaker:inst3|preclk speaker:inst3|\genspks:count11[4] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.96 % ) " "Info: Total cell delay = 3.115 ns ( 41.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.308 ns ( 58.04 % ) " "Info: Total interconnect delay = 4.308 ns ( 58.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "7.423 ns" { clk5MHz speaker:inst3|preclk speaker:inst3|\genspks:count11[4] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "7.423 ns" { clk5MHz clk5MHz~out0 speaker:inst3|preclk speaker:inst3|\genspks:count11[4] } { 0.000ns 0.000ns 0.602ns 3.706ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk5MHz source 7.423 ns - Longest register " "Info: - Longest clock path from clock \"clk5MHz\" to source register is 7.423 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk5MHz 1 CLK PIN_17 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 5; CLK Node = 'clk5MHz'" { } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { clk5MHz } "NODE_NAME" } } { "music_1.bdf" "" { Schematic "E:/design/junior/music_1/music_1.bdf" { { 0 352 520 16 "clk5MHz" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.935 ns) 3.006 ns speaker:inst3\|preclk 2 REG LC_X26_Y6_N5 12 " "Info: 2: + IC(0.602 ns) + CELL(0.935 ns) = 3.006 ns; Loc. = LC_X26_Y6_N5; Fanout = 12; REG Node = 'speaker:inst3\|preclk'" { } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.537 ns" { clk5MHz speaker:inst3|preclk } "NODE_NAME" } } { "speaker.vhd" "" { Text "E:/design/junior/music_1/speaker.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.706 ns) + CELL(0.711 ns) 7.423 ns speaker:inst3\|\\genspks:count11\[3\] 3 REG LC_X20_Y6_N8 4 " "Info: 3: + IC(3.706 ns) + CELL(0.711 ns) = 7.423 ns; Loc. = LC_X20_Y6_N8; Fanout = 4; REG Node = 'speaker:inst3\|\\genspks:count11\[3\]'" { } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.417 ns" { speaker:inst3|preclk speaker:inst3|\genspks:count11[3] } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.96 % ) " "Info: Total cell delay = 3.115 ns ( 41.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.308 ns ( 58.04 % ) " "Info: Total interconnect delay = 4.308 ns ( 58.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "7.423 ns" { clk5MHz speaker:inst3|preclk speaker:inst3|\genspks:count11[3] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "7.423 ns" { clk5MHz clk5MHz~out0 speaker:inst3|preclk speaker:inst3|\genspks:count11[3] } { 0.000ns 0.000ns 0.602ns 3.706ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "7.423 ns" { clk5MHz speaker:inst3|preclk speaker:inst3|\genspks:count11[4] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "7.423 ns" { clk5MHz clk5MHz~out0 speaker:inst3|preclk speaker:inst3|\genspks:count11[4] } { 0.000ns 0.000ns 0.602ns 3.706ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "7.423 ns" { clk5MHz speaker:inst3|preclk speaker:inst3|\genspks:count11[3] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "7.423 ns" { clk5MHz clk5MHz~out0 speaker:inst3|preclk speaker:inst3|\genspks:count11[3] } { 0.000ns 0.000ns 0.602ns 3.706ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.651 ns" { speaker:inst3|\genspks:count11[3] speaker:inst3|Equal1~98 speaker:inst3|Equal1~101 speaker:inst3|\genspks:count11[4] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "4.651 ns" { speaker:inst3|\genspks:count11[3] speaker:inst3|Equal1~98 speaker:inst3|Equal1~101 speaker:inst3|\genspks:count11[4] } { 0.000ns 1.291ns 0.182ns 1.249ns } { 0.000ns 0.590ns 0.114ns 1.225ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "7.423 ns" { clk5MHz speaker:inst3|preclk speaker:inst3|\genspks:count11[4] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "7.423 ns" { clk5MHz clk5MHz~out0 speaker:inst3|preclk speaker:inst3|\genspks:count11[4] } { 0.000ns 0.000ns 0.602ns 3.706ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "7.423 ns" { clk5MHz speaker:inst3|preclk speaker:inst3|\genspks:count11[3] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "7.423 ns" { clk5MHz clk5MHz~out0 speaker:inst3|preclk speaker:inst3|\genspks:count11[3] } { 0.000ns 0.000ns 0.602ns 3.706ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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