📄 music_rom_stop.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity music_rom_stop is
port(clk:in std_logic;
index:out std_logic_vector(3 downto 0));
end entity;
architecture bhv of music_rom_stop is
component data_rom
port( address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );
end component;
--subtype word is integer range 0 to 15;
--type memory is array(0 to 523)of word;
--signal rom: memory;
signal clk_cnt: integer range 0 to 333;
signal clk_4hz:std_logic;
signal adr:integer range 0 to 270;
signal adr1:std_logic_vector(8 downto 0);
begin
divide:process(clk)
begin
if(clk'event and clk='1')then
if clk_cnt=333 then clk_cnt<=0;clk_4hz<='1';
else clk_cnt<=clk_cnt+1;clk_4hz<='0';
end if;
end if;
end process;
cnt:process(clk_4hz)
begin
if adr=270 then adr<=0;
else
if(clk_4hz'event and clk_4hz='1')then
adr<=adr+1;
end if;
end if;
end process;
adr1<=conv_std_logic_vector(adr,9);
u1:data_rom port map (address=>adr1,q=>index,clock=>clk_4hz);
end;
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