f50k.sim.qmsg

VHDL产生时钟50分频程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 03 10:36:09 2008 " "Info: Processing started: Sun Aug 03 10:36:09 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off f50k -c f50k " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off f50k -c f50k" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISDB_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" { { "Info" "ISDB_SOURCE_VECTOR_FILE_BACKUP" "f50k.vwf f50k.sim_ori.vwf " "Info: A backup of f50k.vwf called f50k.sim_ori.vwf is created in the db folder" {  } {  } 0 0 "A backup of %1!s! called %2!s! is created in the db folder" 0 0}  } {  } 0 0 "Overwriting simulation input file with simulation results" 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "load " "Warning: Ignored node in vector source file. Can't find corresponding node name \"load\" in design." {  } { { "E:/FPGA资料/f50k/f50k/f50k.vwf" "" { Waveform "E:/FPGA资料/f50k/f50k/f50k.vwf" "load" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|f50k\|temp\[0\] " "Info: Register: \|f50k\|temp\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|f50k\|temp\[5\] " "Info: Register: \|f50k\|temp\[5\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|f50k\|temp\[3\] " "Info: Register: \|f50k\|temp\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|f50k\|temp\[4\] " "Info: Register: \|f50k\|temp\[4\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|f50k\|temp\[8\] " "Info: Register: \|f50k\|temp\[8\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|f50k\|c3 " "Info: Register: \|f50k\|c3" {  } {  } 0 0 "Register: %1!s!" 0 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     98.95 % " "Info: Simulation coverage is      98.95 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "9894701 " "Info: Number of transitions in simulation is 9894701" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "f50k.vwf " "Info: Vector file f50k.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." {  } {  } 0 0 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 1  Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 03 10:45:56 2008 " "Info: Processing ended: Sun Aug 03 10:45:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:09:48 " "Info: Elapsed time: 00:09:48" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}