f50k.map.summary

来自「VHDL产生时钟50分频程序」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Sat Aug 02 16:30:31 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : f50k
Top-level Entity Name : f50k
Family : ACEX1K
Total logic elements : 254
Total pins : 10
Total memory bits : 0
Total PLLs : 0