f50k.map.eqn

VHDL产生时钟50分频程序

A1L473 = !temp[2] & (m[0] # !b);


--A1L663 is temp~1116
--operation mode is normal

A1L663 = b & (m[1] & (temp[1] # !m[0]) # !m[1] & (m[0])) # !b & temp[1];

--A1L573 is temp~1137
--operation mode is normal

A1L573 = b & (m[1] & (temp[1] # !m[0]) # !m[1] & (m[0])) # !b & temp[1];


--C3_unreg_res_node[4] is lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[4]
--operation mode is normal

C3_unreg_res_node[4] = E9_cout[3] $ y2[4];

--C3L3 is lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[4]~9
--operation mode is normal

C3L3 = E9_cout[3] $ y2[4];


--q is q
--operation mode is normal

q_lut_out = !c3;
q = DFFEA(q_lut_out, clk1, , , , A1L21, reset);

--A1L223Q is q~1
--operation mode is normal

A1L223Q = q;


--clk1 is clk1
--operation mode is normal

clk1_lut_out = !reset & (clk1 $ !A1L523);
clk1 = DFFEA(clk1_lut_out, clk, , , , , );

--A1L61Q is clk1~94
--operation mode is normal

A1L61Q = clk1;


--contl is contl
--operation mode is normal

contl_lut_out = !contl;
contl = DFFEA(contl_lut_out, clk1, , , , , );

--A1L02Q is contl~1
--operation mode is normal

A1L02Q = contl;


--reg is reg
--operation mode is normal

reg_lut_out = q;
reg = DFFEA(reg_lut_out, clk1, , , A1L533, , );

--A1L633Q is reg~2
--operation mode is normal

A1L633Q = reg;


--m_reg[0] is m_reg[0]
--operation mode is normal

m_reg[0]_lut_out = m[0];
m_reg[0] = DFFEA(m_reg[0]_lut_out, clk2, , , , , );

--A1L23Q is m_reg[0]~2
--operation mode is normal

A1L23Q = m_reg[0];


--m_reg[1] is m_reg[1]
--operation mode is normal

m_reg[1]_lut_out = m[1];
m_reg[1] = DFFEA(m_reg[1]_lut_out, clk2, , , , , );

--A1L43Q is m_reg[1]~3
--operation mode is normal

A1L43Q = m_reg[1];


--c3 is c3
--operation mode is normal

c3_lut_out = !c2;
c3 = DFFEA(c3_lut_out, clk1, !reset, , , , );

--A1L31Q is c3~2
--operation mode is normal

A1L31Q = c3;


--y1[4] is y1[4]
--operation mode is normal

y1[4]_lut_out = A1L523 & E21_cs_buffer[4] & (!reset);
y1[4] = DFFEA(y1[4]_lut_out, clk, , , , , );

--A1L683Q is y1[4]~835
--operation mode is normal

A1L683Q = y1[4];


--y1[3] is y1[3]
--operation mode is normal

y1[3]_lut_out = A1L523 & E21_cs_buffer[3] & (!reset);
y1[3] = DFFEA(y1[3]_lut_out, clk, , , , , );

--A1L483Q is y1[3]~836
--operation mode is normal

A1L483Q = y1[3];


--y1[2] is y1[2]
--operation mode is normal

y1[2]_lut_out = reset # E21_cs_buffer[2];
y1[2] = DFFEA(y1[2]_lut_out, clk, , , , , );

--A1L283Q is y1[2]~837
--operation mode is normal

A1L283Q = y1[2];


--y1[1] is y1[1]
--operation mode is normal

y1[1]_lut_out = reset # E21_cs_buffer[1];
y1[1] = DFFEA(y1[1]_lut_out, clk, , , , , );

--A1L083Q is y1[1]~838
--operation mode is normal

A1L083Q = y1[1];


--A1L423 is reduce_nor~131
--operation mode is normal

A1L423 = y1[4] # y1[3] # !y1[1] # !y1[2];

--A1L923 is reduce_nor~142
--operation mode is normal

A1L923 = y1[4] # y1[3] # !y1[1] # !y1[2];


--y1[13] is y1[13]
--operation mode is normal

y1[13]_lut_out = A1L523 & C4_unreg_res_node[13] & (!reset);
y1[13] = DFFEA(y1[13]_lut_out, clk, , , , , );

--A1L404Q is y1[13]~839
--operation mode is normal

A1L404Q = y1[13];


--y1[0] is y1[0]
--operation mode is up_dn_cntr

y1[0]_lut_out = reset # !y1[0];
y1[0] = DFFEA(y1[0]_lut_out, clk, , , , , );

--A1L873Q is y1[0]~840
--operation mode is up_dn_cntr

A1L873Q = y1[0];

--E21_cout[0] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is up_dn_cntr

E21_cout[0] = CARRY(y1[0]);


--A1L523 is reduce_nor~133
--operation mode is normal

A1L523 = A1L423 # y1[13] # !y1[0] # !A1L723;

--A1L033 is reduce_nor~143
--operation mode is normal

A1L033 = A1L423 # y1[13] # !y1[0] # !A1L723;


--c2 is c2
--operation mode is normal

c2_lut_out = c1;
c2 = DFFEA(c2_lut_out, clk1, !reset, , , , );

--A1L01Q is c2~1
--operation mode is normal

A1L01Q = c2;


--E21_cs_buffer[4] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

E21_cs_buffer[4] = y1[4] $ (E21_cout[3]);

--E21L32 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~184
--operation mode is arithmetic

E21L32 = y1[4] $ (E21_cout[3]);

--E21_cout[4] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

E21_cout[4] = CARRY(y1[4] & (E21_cout[3]));


--E21_cs_buffer[3] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

E21_cs_buffer[3] = y1[3] $ (E21_cout[2]);

--E21L12 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~185
--operation mode is arithmetic

E21L12 = y1[3] $ (E21_cout[2]);

--E21_cout[3] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

E21_cout[3] = CARRY(y1[3] & (E21_cout[2]));


--E21_cs_buffer[2] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

E21_cs_buffer[2] = y1[2] $ (E21_cout[1]);

--E21L91 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~186
--operation mode is arithmetic

E21L91 = y1[2] $ (E21_cout[1]);

--E21_cout[2] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

E21_cout[2] = CARRY(y1[2] & (E21_cout[1]));


--E21_cs_buffer[1] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

E21_cs_buffer[1] = y1[1] $ (E21_cout[0]);

--E21L71 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~187
--operation mode is arithmetic

E21L71 = y1[1] $ (E21_cout[0]);

--E21_cout[1] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

E21_cout[1] = CARRY(y1[1] & (E21_cout[0]));


--c1 is c1
--operation mode is normal

c1_lut_out = c3 $ !c2;
c1 = DFFEA(c1_lut_out, clk1, !reset, , , , );

--A1L8Q is c1~1
--operation mode is normal

A1L8Q = c1;


--E21_cs_buffer[12] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

E21_cs_buffer[12] = y1[12] $ (E21_cout[11]);

--E21L93 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~188
--operation mode is arithmetic

E21L93 = y1[12] $ (E21_cout[11]);

--E21_cout[12] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

E21_cout[12] = CARRY(y1[12] & (E21_cout[11]));


--C4_unreg_res_node[13] is lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[13]
--operation mode is normal

C4_unreg_res_node[13] = E21_cout[12] $ y1[13];

--C4L3 is lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[13]~27
--operation mode is normal

C4L3 = E21_cout[12] $ y1[13];


--y1[8] is y1[8]
--operation mode is normal

y1[8]_lut_out = reset # A1L523 & E21_cs_buffer[8];
y1[8] = DFFEA(y1[8]_lut_out, clk, , , , , );

--A1L493Q is y1[8]~841
--operation mode is normal

A1L493Q = y1[8];


--y1[7] is y1[7]
--operation mode is normal

y1[7]_lut_out = reset # A1L523 & E21_cs_buffer[7];
y1[7] = DFFEA(y1[7]_lut_out, clk, , , , , );

--A1L293Q is y1[7]~842
--operation mode is normal

A1L293Q = y1[7];


--y1[6] is y1[6]
--operation mode is normal

y1[6]_lut_out = A1L523 & E21_cs_buffer[6] & (!reset);
y1[6] = DFFEA(y1[6]_lut_out, clk, , , , , );

--A1L093Q is y1[6]~843
--operation mode is normal

A1L093Q = y1[6];


--y1[5] is y1[5]
--operation mode is normal

y1[5]_lut_out = A1L523 & E21_cs_buffer[5] & (!reset);
y1[5] = DFFEA(y1[5]_lut_out, clk, , , , , );

--A1L883Q is y1[5]~844
--operation mode is normal

A1L883Q = y1[5];


--A1L623 is reduce_nor~137
--operation mode is normal

A1L623 = y1[8] & y1[7] & !y1[6] & !y1[5];

--A1L133 is reduce_nor~144
--operation mode is normal

A1L133 = y1[8] & y1[7] & !y1[6] & !y1[5];

--A1L233 is reduce_nor~145
--operation mode is normal

A1L233 = y1[8] & y1[7] & !y1[6] & !y1[5];


--y1[12] is y1[12]
--operation mode is normal

y1[12]_lut_out = reset # A1L523 & E21_cs_buffer[12];
y1[12] = DFFEA(y1[12]_lut_out, clk, , , , , );

--A1L204Q is y1[12]~845
--operation mode is normal

A1L204Q = y1[12];


--y1[9] is y1[9]
--operation mode is normal

y1[9]_lut_out = reset # A1L523 & E21_cs_buffer[9];
y1[9] = DFFEA(y1[9]_lut_out, clk, , , , , );

--A1L693Q is y1[9]~846
--operation mode is normal

A1L693Q = y1[9];


--y1[11] is y1[11]
--operation mode is normal

y1[11]_lut_out = E21_cs_buffer[11] & A1L523 & (!reset);
y1[11] = DFFEA(y1[11]_lut_out, clk, , , , , );

--A1L004Q is y1[11]~847
--operation mode is normal

A1L004Q = y1[11];


--y1[10] is y1[10]
--operation mode is normal

y1[10]_lut_out = A1L523 & E21_cs_buffer[10] & (!reset);
y1[10] = DFFEA(y1[10]_lut_out, clk, , , , , );

--A1L893Q is y1[10]~848
--operation mode is normal

A1L893Q = y1[10];


--A1L723 is reduce_nor~139
--operation mode is normal

A1L723 = (y1[12] & y1[9] & !y1[11] & !y1[10]) & CASCADE(A1L233);

--A1L333 is reduce_nor~146
--operation mode is normal

A1L333 = (y1[12] & y1[9] & !y1[11] & !y1[10]) & CASCADE(A1L233);


--E21_cs_buffer[8] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

E21_cs_buffer[8] = y1[8] $ (E21_cout[7]);

--E21L13 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~189
--operation mode is arithmetic

E21L13 = y1[8] $ (E21_cout[7]);

--E21_cout[8] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

E21_cout[8] = CARRY(y1[8] & (E21_cout[7]));


--E21_cs_buffer[7] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

E21_cs_buffer[7] = y1[7] $ (E21_cout[6]);

--E21L92 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~190
--operation mode is arithmetic

E21L92 = y1[7] $ (E21_cout[6]);

--E21_cout[7] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

E21_cout[7] = CARRY(y1[7] & (E21_cout[6]));


--E21_cs_buffer[6] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

E21_cs_buffer[6] = y1[6] $ (E21_cout[5]);

--E21L72 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~191
--operation mode is arithmetic

E21L72 = y1[6] $ (E21_cout[5]);

--E21_cout[6] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

E21_cout[6] = CARRY(y1[6] & (E21_cout[5]));


--E21_cs_buffer[5] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

E21_cs_buffer[5] = y1[5] $ (E21_cout[4]);

--E21L52 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~192
--operation mode is arithmetic

E21L52 = y1[5] $ (E21_cout[4]);

--E21_cout[5] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

E21_cout[5] = CARRY(y1[5] & (E21_cout[4]));


--E21_cs_buffer[9] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

E21_cs_buffer[9] = y1[9] $ (E21_cout[8]);

--E21L33 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~193
--operation mode is arithmetic

E21L33 = y1[9] $ (E21_cout[8]);

--E21_cout[9] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

E21_cout[9] = CARRY(y1[9] & (E21_cout[8]));


--E21_cs_buffer[11] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

E21_cs_buffer[11] = y1[11] $ (E21_cout[10]);

--E21L73 is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~194
--operation mode is arithmetic

E21L73 = y1[11] $ (E21_cout[10]);

--E21_cout[11] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

E21_cout[11] = CARRY(y1[11] & (E21_cout[10]));


--E21_cs_buffer[10] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer: