dianzhen.rpt

点阵汉字显示的VHDL原程序.综合实验课程的程序,完全可以用的 希望大家支持啊

-- Node name is 'ldob5' 
-- Equation name is 'ldob5', location is LC021, type is output.
 ldob5   = LCELL( _EQ039 $  VCC);
  _EQ039 = !_LC098 &  _X009;
  _X009  = EXP( count10 & !count11 &  count12);

-- Node name is 'ldob6' 
-- Equation name is 'ldob6', location is LC017, type is output.
 ldob6   = LCELL( _EQ040 $  VCC);
  _EQ040 = !_LC120 &  _X010;
  _X010  = EXP(!count10 &  count11 &  count12);

-- Node name is 'ldob7' 
-- Equation name is 'ldob7', location is LC045, type is output.
 ldob7   = LCELL( _EQ041 $  VCC);
  _EQ041 = !_LC128 &  _X011;
  _X011  = EXP( count10 &  count11 &  count12);

-- Node name is '|lpm_add_sub:748|addcore:adder|addcore:adder0|cout_node' from file "addcore.tdf" line 165, column 5
-- Equation name is '_LC119', type is buried 
_LC119   = LCELL( _EQ042 $  GND);
  _EQ042 =  count0 &  count1 &  count2 &  count3 &  count4 &  count5 & 
              count6 &  count7;

-- Node name is '|lpm_add_sub:748|addcore:adder|addcore:adder1|cout_node' from file "addcore.tdf" line 165, column 5
-- Equation name is '_LC034', type is buried 
_LC034   = LCELL( _EQ043 $  GND);
  _EQ043 =  count0 &  count1 &  count2 &  count3 &  count4 &  count5 & 
              count6 &  count7 &  count8 &  count9 &  count10 &  count11 & 
              count12 &  count13 &  count14 &  count15;

-- Node name is '~732~1' 
-- Equation name is '~732~1', location is LC128, type is buried.
-- synthesized logic cell 
_LC128   = LCELL( _EQ044 $  GND);
  _EQ044 =  count10 &  count11 &  count12 &  _LC033 &  _X011;
  _X011  = EXP( count10 &  count11 &  count12);

-- Node name is '~733~1' 
-- Equation name is '~733~1', location is LC120, type is buried.
-- synthesized logic cell 
_LC120   = LCELL( _EQ045 $  GND);
  _EQ045 =  count11 &  count12 &  _LC022 &  _X010 &  _X011;
  _X010  = EXP(!count10 &  count11 &  count12);
  _X011  = EXP( count10 &  count11 &  count12);

-- Node name is '~734~1' 
-- Equation name is '~734~1', location is LC098, type is buried.
-- synthesized logic cell 
_LC098   = LCELL( _EQ046 $  GND);
  _EQ046 =  count10 &  count12 &  _LC023 &  _X009 &  _X010 &  _X011
         #  count11 &  count12 &  _LC023 &  _X009 &  _X010 &  _X011;
  _X009  = EXP( count10 & !count11 &  count12);
  _X010  = EXP(!count10 &  count11 &  count12);
  _X011  = EXP( count10 &  count11 &  count12);

-- Node name is '~735~1' 
-- Equation name is '~735~1', location is LC112, type is buried.
-- synthesized logic cell 
_LC112   = LCELL( _EQ047 $  GND);
  _EQ047 =  count12 &  _LC026 &  _X008 &  _X009 &  _X010 &  _X011;
  _X008  = EXP(!count10 & !count11 &  count12);
  _X009  = EXP( count10 & !count11 &  count12);
  _X010  = EXP(!count10 &  count11 &  count12);
  _X011  = EXP( count10 &  count11 &  count12);

-- Node name is '~736~1' 
-- Equation name is '~736~1', location is LC108, type is buried.
-- synthesized logic cell 
_LC108   = LCELL( _EQ048 $  GND);
  _EQ048 =  count10 &  count11 &  _LC027 &  _X007 &  _X008 &  _X009 &  _X010 & 
              _X011
         #  count12 &  _LC027 &  _X007 &  _X008 &  _X009 &  _X010 &  _X011;
  _X007  = EXP( count10 &  count11 & !count12);
  _X008  = EXP(!count10 & !count11 &  count12);
  _X009  = EXP( count10 & !count11 &  count12);
  _X010  = EXP(!count10 &  count11 &  count12);
  _X011  = EXP( count10 &  count11 &  count12);

-- Node name is '~737~1' 
-- Equation name is '~737~1', location is LC102, type is buried.
-- synthesized logic cell 
_LC102   = LCELL( _EQ049 $  GND);
  _EQ049 =  count11 &  _LC010 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 & 
              _X011
         #  count12 &  _LC010 &  _X006 &  _X007 &  _X008 &  _X009 &  _X010 & 
              _X011;
  _X006  = EXP(!count10 &  count11 & !count12);
  _X007  = EXP( count10 &  count11 & !count12);
  _X008  = EXP(!count10 & !count11 &  count12);
  _X009  = EXP( count10 & !count11 &  count12);
  _X010  = EXP(!count10 &  count11 &  count12);
  _X011  = EXP( count10 &  count11 &  count12);

-- Node name is '~738~1' 
-- Equation name is '~738~1', location is LC100, type is buried.
-- synthesized logic cell 
_LC100   = LCELL( _EQ050 $  GND);
  _EQ050 =  count10 &  _LC012 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 & 
              _X010 &  _X011
         #  count11 &  _LC012 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 & 
              _X010 &  _X011
         #  count12 &  _LC012 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 & 
              _X010 &  _X011;
  _X005  = EXP( count10 & !count11 & !count12);
  _X006  = EXP(!count10 &  count11 & !count12);
  _X007  = EXP( count10 &  count11 & !count12);
  _X008  = EXP(!count10 & !count11 &  count12);
  _X009  = EXP( count10 & !count11 &  count12);
  _X010  = EXP(!count10 &  count11 &  count12);
  _X011  = EXP( count10 &  count11 &  count12);

-- Node name is '~739~1' 
-- Equation name is '~739~1', location is LC103, type is buried.
-- synthesized logic cell 
_LC103   = LCELL( _EQ051 $  GND);
  _EQ051 =  _LC014 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 & 
              _X010 &  _X011;
  _X004  = EXP(!count10 & !count11 & !count12);
  _X005  = EXP( count10 & !count11 & !count12);
  _X006  = EXP(!count10 &  count11 & !count12);
  _X007  = EXP( count10 &  count11 & !count12);
  _X008  = EXP(!count10 & !count11 &  count12);
  _X009  = EXP( count10 & !count11 &  count12);
  _X010  = EXP(!count10 &  count11 &  count12);
  _X011  = EXP( count10 &  count11 &  count12);

-- Node name is '~740~1' 
-- Equation name is '~740~1', location is LC033, type is buried.
-- synthesized logic cell 
_LC033   = LCELL( _EQ052 $  VCC);
  _EQ052 = !_LC128 &  _X011;
  _X011  = EXP( count10 &  count11 &  count12);

-- Node name is '~741~1' 
-- Equation name is '~741~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ053 $  VCC);
  _EQ053 = !_LC120 &  _X010;
  _X010  = EXP(!count10 &  count11 &  count12);

-- Node name is '~742~1' 
-- Equation name is '~742~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ054 $  VCC);
  _EQ054 = !_LC098 &  _X009;
  _X009  = EXP( count10 & !count11 &  count12);

-- Node name is '~743~1' 
-- Equation name is '~743~1', location is LC026, type is buried.
-- synthesized logic cell 
_LC026   = LCELL( _EQ055 $  VCC);
  _EQ055 = !_LC112 &  _X008;
  _X008  = EXP(!count10 & !count11 &  count12);

-- Node name is '~744~1' 
-- Equation name is '~744~1', location is LC027, type is buried.
-- synthesized logic cell 
_LC027   = LCELL( _EQ056 $  VCC);
  _EQ056 = !_LC108 &  _X007;
  _X007  = EXP( count10 &  count11 & !count12);

-- Node name is '~745~1' 
-- Equation name is '~745~1', location is LC010, type is buried.
-- synthesized logic cell 
_LC010   = LCELL( _EQ057 $  VCC);
  _EQ057 = !_LC102 &  _X006;
  _X006  = EXP(!count10 &  count11 & !count12);

-- Node name is '~746~1' 
-- Equation name is '~746~1', location is LC012, type is buried.
-- synthesized logic cell 
_LC012   = LCELL( _EQ058 $  VCC);
  _EQ058 = !_LC100 &  _X005;
  _X005  = EXP( count10 & !count11 & !count12);

-- Node name is '~747~1' 
-- Equation name is '~747~1', location is LC014, type is buried.
-- synthesized logic cell 
_LC014   = LCELL( _EQ059 $  VCC);
  _EQ059 = !_LC103 &  _X004;
  _X004  = EXP(!count10 & !count11 & !count12);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X004 occurs in LABs A, G
--    _X005 occurs in LABs A, G
--    _X006 occurs in LABs A, G
--    _X007 occurs in LABs B, G
--    _X008 occurs in LABs B, G
--    _X009 occurs in LABs B, G
--    _X010 occurs in LABs B, G, H
--    _X011 occurs in LABs C, G, H




Project Information                                   g:\max2work\dianzhen.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 7,256K