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📄 dianzhen.rpt

📁 点阵汉字显示的VHDL原程序.综合实验课程的程序,完全可以用的 希望大家支持啊
💻 RPT
📖 第 1 页 / 共 4 页
字号:
   -     39    C       TFFE   +  t        0      0   0    0   15    0    3  count22 (:61)
 (28)    40    C       TFFE   +  t        0      0   0    0   14    0    4  count21 (:62)
   -     47    C       TFFE   +  t        0      0   0    0   13    0    5  count20 (:63)
   -     41    C       TFFE   +  t        0      0   0    0   12    0    6  count19 (:64)
   -     42    C       TFFE   +  t        0      0   0    0   11    0    7  count18 (:65)
 (27)    43    C       TFFE   +  t        0      0   0    0   17    0    8  count17 (:66)
   -     44    C       TFFE   +  t        0      0   0    0   16    0    9  count16 (:67)
 (24)    46    C       TFFE   +  t        0      0   0    0   15    0   10  count15 (:68)
 (23)    48    C       TFFE   +  t        0      0   0    0   14    0   11  count14 (:69)
 (29)    38    C       TFFE   +  t        0      0   0    0   13    0   12  count13 (:70)
   -    116    H       TFFE   +  t        0      0   0    0   12   16   29  count12 (:71)
   -    113    H       TFFE   +  t        0      0   0    0   11   16   30  count11 (:72)
   -    114    H       TFFE   +  t        0      0   0    0   10   16   31  count10 (:73)
   -    121    H       TFFE   +  t        0      0   0    0    9    0   16  count9 (:74)
   -    122    H       TFFE   +  t        0      0   0    0    8    0   17  count8 (:75)
 (80)   126    H       TFFE   +  t        0      0   0    0    7    0   12  count7 (:76)
 (73)   115    H       TFFE   +  t        0      0   0    0    6    0   13  count6 (:77)
   -    127    H       TFFE   +  t        0      0   0    0    5    0   14  count5 (:78)
   -    124    H       TFFE   +  t        0      0   0    0    4    0   15  count4 (:79)
 (77)   123    H       TFFE   +  t        0      0   0    0    3    0   16  count3 (:80)
 (75)   118    H       TFFE   +  t        0      0   0    0    2    0   17  count2 (:81)
 (79)   125    H       TFFE   +  t        0      0   0    0    1    0   18  count1 (:82)
   -      9    A       TFFE   +  t        0      0   0    0    0    0   19  count0 (:83)
 (81)   128    H       SOFT    s t        1      1   0    0    4    1    1  ~732~1
 (76)   120    H       SOFT    s t        2      2   0    0    4    1    1  ~733~1
   -     98    G       SOFT    s t        3      3   0    0    4    1    1  ~734~1
 (71)   112    G       SOFT    s t        4      4   0    0    4    1    1  ~735~1
   -    108    G       SOFT    s t        5      5   0    0    4    1    1  ~736~1
   -    102    G       SOFT    s t        6      6   0    0    4    1    1  ~737~1
   -    100    G       SOFT    s t        7      7   0    0    4    1    1  ~738~1
   -    103    G       SOFT    s t        8      8   0    0    4    1    1  ~739~1
   -     33    C      LCELL    s t        1      1   0    0    4    0    1  ~740~1
   -     22    B      LCELL    s t        1      1   0    0    4    0    1  ~741~1
   -     23    B      LCELL    s t        1      1   0    0    4    0    1  ~742~1
   -     26    B      LCELL    s t        1      1   0    0    4    0    1  ~743~1
 (16)    27    B      LCELL    s t        1      1   0    0    4    0    1  ~744~1
   -     10    A      LCELL    s t        1      1   0    0    4    0    1  ~745~1
   -     12    A      LCELL    s t        1      1   0    0    4    0    1  ~746~1
  (5)    14    A      LCELL    s t        1      1   0    0    4    0    1  ~747~1


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                          g:\max2work\dianzhen.rpt
dianzhen

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                       Logic cells placed in LAB 'A'
        +------------- LC13 ldob0
        | +----------- LC8 ldob1
        | | +--------- LC5 ldob2
        | | | +------- LC9 count0
        | | | | +----- LC10 ~745~1
        | | | | | +--- LC12 ~746~1
        | | | | | | +- LC14 ~747~1
        | | | | | | | 
        | | | | | | |   Other LABs fed by signals
        | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'A':

Pin
83   -> - - - - - - - | - - - - - - - - | <-- clock
LC116-> * * * - * * * | * * * - - * * * | <-- count12
LC113-> * * * - * * * | * * * - - * * * | <-- count11
LC114-> * * * - * * * | * * * - - * * * | <-- count10
LC102-> - - * - * - - | * - - - - - - - | <-- ~737~1
LC100-> - * - - - * - | * - - - - - - - | <-- ~738~1
LC103-> * - - - - - * | * - - - - - - - | <-- ~739~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          g:\max2work\dianzhen.rpt
dianzhen

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC29 ldob3
        | +------------- LC25 ldob4
        | | +----------- LC21 ldob5
        | | | +--------- LC17 ldob6
        | | | | +------- LC22 ~741~1
        | | | | | +----- LC23 ~742~1
        | | | | | | +--- LC26 ~743~1
        | | | | | | | +- LC27 ~744~1
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'B':

Pin
83   -> - - - - - - - - | - - - - - - - - | <-- clock
LC116-> * * * * * * * * | * * * - - * * * | <-- count12
LC113-> * * * * * * * * | * * * - - * * * | <-- count11
LC114-> * * * * * * * * | * * * - - * * * | <-- count10
LC120-> - - - * * - - - | - * - - - - - - | <-- ~733~1
LC98 -> - - * - - * - - | - * - - - - - - | <-- ~734~1
LC112-> - * - - - - * - | - * - - - - - - | <-- ~735~1
LC108-> * - - - - - - * | - * - - - - - - | <-- ~736~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          g:\max2work\dianzhen.rpt
dianzhen

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC45 ldob7
        | +----------------------------- LC34 |lpm_add_sub:748|addcore:adder|addcore:adder1|cout_node
        | | +--------------------------- LC37 count25
        | | | +------------------------- LC35 count24
        | | | | +----------------------- LC36 count23
        | | | | | +--------------------- LC39 count22
        | | | | | | +------------------- LC40 count21
        | | | | | | | +----------------- LC47 count20
        | | | | | | | | +--------------- LC41 count19
        | | | | | | | | | +------------- LC42 count18
        | | | | | | | | | | +----------- LC43 count17
        | | | | | | | | | | | +--------- LC44 count16
        | | | | | | | | | | | | +------- LC46 count15
        | | | | | | | | | | | | | +----- LC48 count14
        | | | | | | | | | | | | | | +--- LC38 count13
        | | | | | | | | | | | | | | | +- LC33 ~740~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'C':
LC34 -> - - * - - - - - - - - - - - - - | - - * - - - - - | <-- |lpm_add_sub:748|addcore:adder|addcore:adder1|cout_node
LC35 -> - - * * - - - - - - - - - - - - | - - * - - * * * | <-- count24
LC36 -> - - * * * - - - - - - - - - - - | - - * - - - - - | <-- count23
LC39 -> - - * * * * - - - - - - - - - - | - - * - - - - - | <-- count22
LC40 -> - - * * * * * - - - - - - - - - | - - * - - - - - | <-- count21
LC47 -> - - * * * * * * - - - - - - - - | - - * - - - - - | <-- count20
LC41 -> - - * * * * * * * - - - - - - - | - - * - - - - - | <-- count19
LC42 -> - - * * * * * * * * - - - - - - | - - * - - - - - | <-- count18
LC43 -> - - * * * * * * * * * - - - - - | - - * - - - - - | <-- count17
LC44 -> - - * * * * * * * * * * - - - - | - - * - - - - - | <-- count16
LC46 -> - * - * * * * * * * * * * - - - | - - * - - - - - | <-- count15
LC48 -> - * - * * * * * * * * * * * - - | - - * - - - - - | <-- count14
LC38 -> - * - * * * * * * * * * * * * - | - - * - - - - - | <-- count13

Pin
83   -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clock
LC119-> - - - * * * * * * * - - - - - - | - - * - - - - - | <-- |lpm_add_sub:748|addcore:adder|addcore:adder0|cout_node
LC116-> * * - * * * * * * * * * * * * * | * * * - - * * * | <-- count12
LC113-> * * - * * * * * * * * * * * * * | * * * - - * * * | <-- count11
LC114-> * * - * * * * * * * * * * * * * | * * * - - * * * | <-- count10
LC121-> - * - * * * * * * * * * * * * - | - - * - - - - * | <-- count9
LC122-> - * - * * * * * * * * * * * * - | - - * - - - - * | <-- count8
LC126-> - * - - - - - - - - * * * * * - | - - * - - - - * | <-- count7
LC115-> - * - - - - - - - - * * * * * - | - - * - - - - * | <-- count6
LC127-> - * - - - - - - - - * * * * * - | - - * - - - - * | <-- count5
LC124-> - * - - - - - - - - * * * * * - | - - * - - - - * | <-- count4
LC123-> - * - - - - - - - - * * * * * - | - - * - - - - * | <-- count3
LC118-> - * - - - - - - - - * * * * * - | - - * - - - - * | <-- count2
LC125-> - * - - - - - - - - * * * * * - | - - * - - - - * | <-- count1
LC9  -> - * - - - - - - - - * * * * * - | - - * - - - - * | <-- count0
LC128-> * - - - - - - - - - - - - - - * | - - * - - - - - | <-- ~732~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          g:\max2work\dianzhen.rpt
dianzhen

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

               Logic cells placed in LAB 'F'
        +----- LC86 ldoa0
        | +--- LC88 ldoa1
        | | +- LC93 ldoa2
        | | | 
        | | |   Other LABs fed by signals
        | | |   that feed LAB 'F'
LC      | | | | A B C D E F G H |     Logic cells that feed LAB 'F':

Pin
83   -> - - - | - - - - - - - - | <-- clock
LC37 -> * * * | - - - - - * * * | <-- count25
LC35 -> * * * | - - * - - * * * | <-- count24
LC116-> * * * | * * * - - * * * | <-- count12
LC113-> * * * | * * * - - * * * | <-- count11
LC114-> * * * | * * * - - * * * | <-- count10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          g:\max2work\dianzhen.rpt
dianzhen

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                             Logic cells placed in LAB 'G'
        +------------------- LC97 ldoa3
        | +----------------- LC101 ldoa4
        | | +--------------- LC105 ldoa5
        | | | +------------- LC109 ldoa6
        | | | | +----------- LC98 ~734~1
        | | | | | +--------- LC112 ~735~1
        | | | | | | +------- LC108 ~736~1
        | | | | | | | +----- LC102 ~737~1
        | | | | | | | | +--- LC100 ~738~1
        | | | | | | | | | +- LC103 ~739~1
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':

Pin
83   -> - - - - - - - - - - | - - - - - - - - | <-- clock
LC37 -> * * * * - - - - - - | - - - - - * * * | <-- count25
LC35 -> * * * * - - - - - - | - - * - - * * * | <-- count24
LC116-> * * * * * * * * * * | * * * - - * * * | <-- count12
LC113-> * * * * * * * * * * | * * * - - * * * | <-- count11
LC114-> * * * * * * * * * * | * * * - - * * * | <-- count10
LC23 -> - - - - * - - - - - | - - - - - - * - | <-- ~742~1
LC26 -> - - - - - * - - - - | - - - - - - * - | <-- ~743~1
LC27 -> - - - - - - * - - - | - - - - - - * - | <-- ~744~1
LC10 -> - - - - - - - * - - | - - - - - - * - | <-- ~745~1
LC12 -> - - - - - - - - * - | - - - - - - * - | <-- ~746~1
LC14 -> - - - - - - - - - * | - - - - - - * - | <-- ~747~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          g:\max2work\dianzhen.rpt
dianzhen

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                         Logic cells placed in LAB 'H'
        +------------------------------- LC117 ldoa7
        | +----------------------------- LC119 |lpm_add_sub:748|addcore:adder|addcore:adder0|cout_node
        | | +--------------------------- LC116 count12
        | | | +------------------------- LC113 count11
        | | | | +----------------------- LC114 count10
        | | | | | +--------------------- LC121 count9
        | | | | | | +------------------- LC122 count8
        | | | | | | | +----------------- LC126 count7
        | | | | | | | | +--------------- LC115 count6
        | | | | | | | | | +------------- LC127 count5
        | | | | | | | | | | +----------- LC124 count4
        | | | | | | | | | | | +--------- LC123 count3
        | | | | | | | | | | | | +------- LC118 count2
        | | | | | | | | | | | | | +----- LC125 count1
        | | | | | | | | | | | | | | +--- LC128 ~732~1
        | | | | | | | | | | | | | | | +- LC120 ~733~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC116-> * - * - - - - - - - - - - - * * | * * * - - * * * | <-- count12
LC113-> * - * * - - - - - - - - - - * * | * * * - - * * * | <-- count11
LC114-> * - * * * - - - - - - - - - * * | * * * - - * * * | <-- count10
LC121-> - - * * * * - - - - - - - - - - | - - * - - - - * | <-- count9
LC122-> - - * * * * * - - - - - - - - - | - - * - - - - * | <-- count8

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