jishu2.v

0-99记数VHDL的源程序,综合实验指导书上的,可以用的 大家下载哦

module jishu2(duan,wei,clk,kongzhi);
input clk;
output [7:0] duan;
output [5:0] wei;
output kongzhi;
reg [7:0] duanreg;
reg [3:0] duanregg;
reg [5:0] weireg;
reg [31:0] counta;
always@(posedge clk)
begin
counta=counta+1;
if(counta[27:24]==4'b1010)
begin
counta[27:0]=28'h0000000;
counta[31:28]=counta[31:28]+1;
if(counta[31:28]==4'b1010)
   counta[31:28]=4'b0000;
end
end
always@(counta[11])
begin
case(counta[11])
1'b0:weireg=6'b111101;
1'b1:weireg=6'b111110;    
endcase
end
always@(counta[11])
begin
case(counta[11])
1'b0:duanregg=counta[31:28];
1'b1:duanregg=counta[27:24];
endcase
end
always@(duanregg)
begin
case(duanregg[3:0])
 4'h0: duanreg = 8'hc0;	
 4'h1: duanreg = 8'hf9;	
 4'h2: duanreg = 8'ha4;	
 4'h3: duanreg = 8'hb0;	
 4'h4: duanreg = 8'h99;	
 4'h5: duanreg = 8'h92;	
 4'h6: duanreg = 8'h82;	
 4'h7: duanreg = 8'hf8;				
 4'h8: duanreg = 8'h80;
 4'h9: duanreg = 8'h90;
endcase
end
assign kongzhi=1;
assign duan=duanreg;
assign wei=weireg;
endmodule