📄 jishu2.rpt
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 clk
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\max2work\jishu2.rpt
jishu2
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
25 45 C OUTPUT s t 1 0 1 0 5 1 0 duan0
22 17 B OUTPUT s t 1 0 1 0 6 1 1 duan1
20 21 B OUTPUT s t 0 0 0 0 5 1 0 duan2
17 25 B OUTPUT s t 1 0 1 0 6 1 1 duan3
15 29 B OUTPUT s t 1 0 1 0 6 1 1 duan4
11 5 A OUTPUT s t 1 0 1 0 6 1 1 duan5
9 8 A OUTPUT s t 1 0 1 0 5 1 0 duan6
6 13 A OUTPUT s t 0 0 0 0 4 1 0 duan7
56 86 F OUTPUT t 0 0 0 0 0 0 0 kongzhi
60 93 F FF + t ! 0 0 0 0 5 0 0 wei0 (~497~1)
63 97 G FF + t 0 0 0 0 5 0 15 wei1 (:497)
65 101 G OUTPUT t 0 0 0 0 0 0 0 wei2
68 105 G OUTPUT t 0 0 0 0 0 0 0 wei3
70 109 G OUTPUT t 0 0 0 0 0 0 0 wei4
74 117 H OUTPUT t 0 0 0 0 0 0 0 wei5
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\max2work\jishu2.rpt
jishu2
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(44) 65 E SOFT t 0 0 0 0 8 0 3 |lpm_add_sub:728|addcore:adder|addcore:adder0|cout_node
- 108 G SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder0|result_node1
(71) 112 G SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder0|result_node2
(64) 99 G SOFT t 0 0 0 0 4 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder0|result_node3
(48) 72 E SOFT t 0 0 0 0 5 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder0|result_node4
- 76 E SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder0|result_node5
- 79 E SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder0|result_node6
(52) 80 E SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder0|result_node7
(50) 75 E SOFT t 0 0 0 0 16 0 7 |lpm_add_sub:728|addcore:adder|addcore:adder1|cout_node
- 74 E SOFT t 0 0 0 0 9 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder1|result_node0
- 78 E SOFT t 0 0 0 0 10 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder1|result_node1
- 66 E SOFT t 0 0 0 0 11 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder1|result_node2
(51) 77 E SOFT t 0 0 0 0 12 2 0 |lpm_add_sub:728|addcore:adder|addcore:adder1|result_node3
(45) 67 E SOFT t 0 0 0 0 13 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder1|result_node4
- 68 E SOFT t 0 0 0 0 14 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder1|result_node5
(46) 69 E SOFT t 0 0 0 0 15 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder1|result_node6
- 70 E SOFT t 0 0 0 0 16 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder1|result_node7
(77) 123 H SOFT t 0 0 0 0 17 0 7 |lpm_add_sub:728|addcore:adder|addcore:adder2|cout_node
- 71 E SOFT t 0 0 0 0 17 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node0
(49) 73 E SOFT t 0 0 0 0 18 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node1
- 124 H SOFT t 0 0 0 0 4 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node2
(80) 126 H SOFT t 0 0 0 0 5 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node3
(81) 128 H SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node4
- 119 H SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node5
(76) 120 H SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node6
(79) 125 H SOFT t 0 0 0 0 9 0 1 |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node7
- 113 H SOFT t 0 0 0 0 18 2 29 |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node0
(41) 49 D SOFT t 0 0 0 0 3 2 29 |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node1
(40) 51 D SOFT t 0 0 0 0 4 2 29 |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node2
- 114 H SOFT t 0 0 0 0 5 2 29 |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node3
- 116 H SOFT t 0 0 0 0 6 0 7 |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node4
(73) 115 H SOFT t 0 0 0 0 7 0 5 |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node5
- 127 H SOFT t 0 0 0 0 8 0 4 |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node6
(75) 118 H SOFT t 0 0 0 0 17 0 2 |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node7
- 98 G SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:729|addcore:adder|addcore:adder0|result_node1
(67) 104 G SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:729|addcore:adder|addcore:adder0|result_node2
- 111 G SOFT t 0 0 0 0 4 0 2 |lpm_add_sub:729|addcore:adder|addcore:adder0|result_node3
- 110 G DFFE + t 1 0 0 0 9 0 2 counta31 (:477)
- 103 G DFFE + t 0 0 0 0 7 0 3 counta30 (:478)
- 102 G DFFE + t 0 0 0 0 8 0 4 counta29 (:479)
- 100 G DFFE + t 0 0 0 0 5 0 5 counta28 (:480)
(58) 91 F DFFE + t 0 0 0 0 4 0 6 counta27 (:481)
- 52 D TFFE + t 0 0 0 0 3 0 7 counta26 (:482)
(69) 107 G DFFE + t 0 0 0 0 4 0 9 counta25 (:483)
- 122 H TFFE + t 0 0 0 0 17 0 10 counta24 (:484)
(10) 6 A DFFE + t 0 0 0 0 5 0 5 counta23 (:485)
(12) 3 A DFFE + t 0 0 0 0 5 0 6 counta22 (:486)
- 2 A DFFE + t 0 0 0 0 5 0 7 counta21 (:487)
- 12 A DFFE + t 0 0 0 0 5 0 8 counta20 (:488)
- 4 A DFFE + t 0 0 0 0 5 0 9 counta19 (:489)
- 15 A DFFE + t 0 0 0 0 5 0 10 counta18 (:490)
- 9 A DFFE + t 0 0 0 0 5 0 11 counta17 (:491)
- 10 A DFFE + t 0 0 0 0 5 0 12 counta16 (:492)
- 60 D DFFE + t 0 0 0 0 5 0 7 counta15 (:493)
(35) 59 D DFFE + t 0 0 0 0 5 0 8 counta14 (:494)
(36) 57 D DFFE + t 0 0 0 0 5 0 9 counta13 (:495)
(39) 53 D DFFE + t 0 0 0 0 5 0 10 counta12 (:496)
- 50 D DFFE + t 0 0 0 0 5 0 12 counta10 (:498)
- 54 D DFFE + t 0 0 0 0 5 0 13 counta9 (:499)
(37) 56 D DFFE + t 0 0 0 0 5 0 14 counta8 (:500)
(33) 64 D DFFE + t 0 0 0 0 5 0 13 counta7 (:501)
- 63 D DFFE + t 0 0 0 0 5 0 14 counta6 (:502)
- 62 D DFFE + t 0 0 0 0 5 0 15 counta5 (:503)
- 90 F DFFE + t 0 0 0 0 5 0 16 counta4 (:504)
- 1 A DFFE + t 0 0 0 0 5 0 17 counta3 (:505)
- 89 F DFFE + t 0 0 0 0 5 0 18 counta2 (:506)
- 84 F DFFE + t 0 0 0 0 5 0 19 counta1 (:507)
- 106 G TFFE + t 0 0 0 0 5 0 20 counta0 (:508)
- 121 H LCELL s t 0 0 0 0 3 8 3 ~525~1
- 55 D LCELL s t 0 0 0 0 3 8 4 ~526~1
- 58 D LCELL s t 0 0 0 0 3 8 4 ~527~1
(34) 61 D LCELL s t 0 0 0 0 3 7 4 ~528~1
(8) 11 A LCELL s t 0 0 0 0 5 1 0 ~679~1~2
- 26 B LCELL s t 0 0 0 0 5 1 0 ~680~1~2
(21) 19 B LCELL s t 0 0 0 0 5 1 0 ~681~1~2
- 18 B LCELL s t 0 0 0 0 4 1 0 ~683~1~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\max2work\jishu2.rpt
jishu2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------- LC5 duan5
| +----------------------- LC8 duan6
| | +--------------------- LC13 duan7
| | | +------------------- LC6 counta23
| | | | +----------------- LC3 counta22
| | | | | +--------------- LC2 counta21
| | | | | | +------------- LC12 counta20
| | | | | | | +----------- LC4 counta19
| | | | | | | | +--------- LC15 counta18
| | | | | | | | | +------- LC9 counta17
| | | | | | | | | | +----- LC10 counta16
| | | | | | | | | | | +--- LC1 counta3
| | | | | | | | | | | | +- LC11 ~679~1~2
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC5 -> * - - - - - - - - - - - * | * - - - - - - - | <-- duan5
LC8 -> - * - - - - - - - - - - - | * - - - - - - - | <-- duan6
LC13 -> - - * - - - - - - - - - - | * - - - - - - - | <-- duan7
LC11 -> * - - - - - - - - - - - - | * - - - - - - - | <-- ~679~1~2
Pin
83 -> - - - - - - - - - - - - - | - - - - - - - - | <-- clk
LC99 -> - - - - - - - - - - - * - | * - - - - - - - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder0|result_node3
LC71 -> - - - - - - - - - - * - - | * - - - - - - - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node0
LC73 -> - - - - - - - - - * - - - | * - - - - - - - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node1
LC124-> - - - - - - - - * - - - - | * - - - - - - - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node2
LC126-> - - - - - - - * - - - - - | * - - - - - - - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node3
LC128-> - - - - - - * - - - - - - | * - - - - - - - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node4
LC119-> - - - - - * - - - - - - - | * - - - - - - - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node5
LC120-> - - - - * - - - - - - - - | * - - - - - - - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node6
LC125-> - - - * - - - - - - - - - | * - - - - - - - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder2|result_node7
LC113-> - - - * * * * * * * * * - | * - - * - * * - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node0
LC49 -> - - - * * * * * * * * * - | * - - * - * * - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node1
LC51 -> - - - * * * * * * * * * - | * - - * - * * - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node2
LC114-> - - - * * * * * * * * * - | * - - * - * * - | <-- |lpm_add_sub:728|addcore:adder|addcore:adder3|result_node3
LC121-> * * * - - - - - - - - - * | * * * - - - - - | <-- ~525~1
LC55 -> * * * - - - - - - - - - * | * * * - - - - - | <-- ~526~1
LC58 -> * * * - - - - - - - - - * | * * * - - - - - | <-- ~527~1
LC61 -> * * - - - - - - - - - - * | * * * - - - - - | <-- ~528~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\max2work\jishu2.rpt
jishu2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------- LC17 duan1
| +----------- LC21 duan2
| | +--------- LC25 duan3
| | | +------- LC29 duan4
| | | | +----- LC26 ~680~1~2
| | | | | +--- LC19 ~681~1~2
| | | | | | +- LC18 ~683~1~2
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'B'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
LC17 -> * - - - - - * | - * - - - - - - | <-- duan1
LC21 -> - * - - - - - | - * - - - - - - | <-- duan2
LC25 -> - - * - - * - | - * - - - - - - | <-- duan3
LC29 -> - - - * * - - | - * - - - - - - | <-- duan4
LC26 -> - - - * - - - | - * - - - - - - | <-- ~680~1~2
LC19 -> - - * - - - - | - * - - - - - - | <-- ~681~1~2
LC18 -> * - - - - - - | - * - - - - - - | <-- ~683~1~2
Pin
83 -> - - - - - - - | - - - - - - - - | <-- clk
LC121-> * * * * * * - | * * * - - - - - | <-- ~525~1
LC55 -> * * * * * * * | * * * - - - - - | <-- ~526~1
LC58 -> * * * * * * * | * * * - - - - - | <-- ~527~1
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