📄 jishu2.rpt
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Project Information d:\max2work\jishu2.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/01/2007 23:25:14
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
jishu2 EPM7128SLC84-15 1 15 0 91 1 71 %
User Pins: 1 15 0
Project Information d:\max2work\jishu2.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'wei5' is stuck at VCC
Warning: Primitive 'wei4' is stuck at VCC
Warning: Primitive 'wei3' is stuck at VCC
Warning: Primitive 'wei2' is stuck at VCC
Warning: Primitive 'kongzhi' is stuck at VCC
Project Information d:\max2work\jishu2.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\max2work\jishu2.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
jishu2@83 clk
jishu2@25 duan0
jishu2@22 duan1
jishu2@20 duan2
jishu2@17 duan3
jishu2@15 duan4
jishu2@11 duan5
jishu2@9 duan6
jishu2@6 duan7
jishu2@56 kongzhi
jishu2@60 wei0
jishu2@63 wei1
jishu2@65 wei2
jishu2@68 wei3
jishu2@70 wei4
jishu2@74 wei5
Project Information d:\max2work\jishu2.rpt
** FILE HIERARCHY **
|lpm_add_sub:728|
|lpm_add_sub:728|addcore:adder|
|lpm_add_sub:728|addcore:adder|addcore:adder3|
|lpm_add_sub:728|addcore:adder|addcore:adder2|
|lpm_add_sub:728|addcore:adder|addcore:adder1|
|lpm_add_sub:728|addcore:adder|addcore:adder0|
|lpm_add_sub:728|altshift:result_ext_latency_ffs|
|lpm_add_sub:728|altshift:carry_ext_latency_ffs|
|lpm_add_sub:728|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:729|
|lpm_add_sub:729|addcore:adder|
|lpm_add_sub:729|addcore:adder|addcore:adder0|
|lpm_add_sub:729|altshift:result_ext_latency_ffs|
|lpm_add_sub:729|altshift:carry_ext_latency_ffs|
|lpm_add_sub:729|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\max2work\jishu2.rpt
jishu2
***** Logic for device 'jishu2' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R R R
E E E E E E E E E E
S S S S V S S S S S S
d E d E d E E C E E E V E E E
u R u R u R R C R R R C R R R
a V a V G a V V I G G G c G V V V C V V V
n E n E N n E E N N N N l N E E E I E E E
5 D 6 D D 7 D D T D D D k D D D D O D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
RESERVED | 12 74 | wei5
VCCIO | 13 73 | RESERVED
#TDI | 14 72 | GND
duan4 | 15 71 | #TDO
RESERVED | 16 70 | wei4
duan3 | 17 69 | RESERVED
RESERVED | 18 68 | wei3
GND | 19 67 | RESERVED
duan2 | 20 66 | VCCIO
RESERVED | 21 65 | wei2
duan1 | 22 EPM7128SLC84-15 64 | RESERVED
#TMS | 23 63 | wei1
RESERVED | 24 62 | #TCK
duan0 | 25 61 | RESERVED
VCCIO | 26 60 | wei0
RESERVED | 27 59 | GND
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | RESERVED
RESERVED | 30 56 | kongzhi
RESERVED | 31 55 | RESERVED
GND | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R R R V R R R G V R R R G R R R R R V
E E E E E C E E E N C E E E N E E E E E C
S S S S S C S S S D C S S S D S S S S S C
E E E E E I E E E I E E E E E E E E I
R R R R R O R R R N R R R R R R R R O
V V V V V V V V T V V V V V V V V
E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\max2work\jishu2.rpt
jishu2
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 13/16( 81%) 3/ 8( 37%) 2/16( 12%) 21/36( 58%)
B: LC17 - LC32 7/16( 43%) 5/ 8( 62%) 3/16( 18%) 11/36( 30%)
C: LC33 - LC48 1/16( 6%) 2/ 8( 25%) 1/16( 6%) 5/36( 13%)
D: LC49 - LC64 16/16(100%) 0/ 8( 0%) 0/16( 0%) 22/36( 61%)
E: LC65 - LC80 16/16(100%) 0/ 8( 0%) 0/16( 0%) 18/36( 50%)
F: LC81 - LC96 6/16( 37%) 3/ 8( 37%) 0/16( 0%) 8/36( 22%)
G: LC97 - LC112 16/16(100%) 5/ 8( 62%) 1/16( 6%) 16/36( 44%)
H: LC113 - LC128 16/16(100%) 1/ 8( 12%) 0/16( 0%) 27/36( 75%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 19/64 ( 29%)
Total logic cells used: 91/128 ( 71%)
Total shareable expanders used: 1/128 ( 1%)
Total Turbo logic cells used: 91/128 ( 71%)
Total shareable expanders not available (n/a): 6/128 ( 4%)
Average fan-in: 6.79
Total fan-in: 618
Total input pins required: 1
Total fast input logic cells required: 0
Total output pins required: 15
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 91
Total flipflops required: 33
Total product terms required: 199
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 1
Synthesized logic cells: 16/ 128 ( 12%)
Device-Specific Information: d:\max2work\jishu2.rpt
jishu2
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
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