reg8.v

来自「寄存器的VHDL源码.可能有点简单 新手大家间量 希望和大家学习」· Verilog 代码 · 共 48 行

//--------------------------------------------------------------------------------------------------
//
// Title       : reg8
// Design      : exp1
// Author      : liwei
// Company     : buaa
//
//-------------------------------------------------------------------------------------------------
//
// File        : reg8.v
// Generated   : Tue Apr 25 21:53:37 2006
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1 ns / 1 ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {reg8}}
module reg8 ( clr ,clk ,DOUT ,D );

input clr ;
wire clr ;
input clk ;
wire clk ;
input [7:0] D ;
wire [7:0] D ;

output [7:0] DOUT ;
reg [7:0] DOUT ;

//}} End of automatically maintained section

// -- edit by liwei -- //
always @ ( posedge clk or posedge clr)
	begin 
		if ( clr == 1'b1)
			DOUT <= 0;
		else DOUT <= D ; 
		end
		
endmodule