verilog_seg7.fit.rpt

Verilog 经典实例

+----------------------------+----------------------+
; Interconnect Resource Type ; Usage                ;
+----------------------------+----------------------+
; C4s                        ; 7 / 2,870 ( < 1 % )  ;
; Direct links               ; 19 / 3,938 ( < 1 % ) ;
; Global clocks              ; 4 / 4 ( 100 % )      ;
; LAB clocks                 ; 6 / 72 ( 8 % )       ;
; LUT chains                 ; 3 / 1,143 ( < 1 % )  ;
; Local interconnects        ; 47 / 3,938 ( 1 % )   ;
; R4s                        ; 23 / 2,832 ( < 1 % ) ;
+----------------------------+----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 7.75) ; Number of LABs  (Total = 8) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 1                           ;
; 2                                          ; 0                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 0                           ;
; 6                                          ; 0                           ;
; 7                                          ; 2                           ;
; 8                                          ; 1                           ;
; 9                                          ; 1                           ;
; 10                                         ; 3                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.13) ; Number of LABs  (Total = 8) ;
+------------------------------------+-----------------------------+
; 1 Async. clear                     ; 3                           ;
; 1 Clock                            ; 6                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 7.75) ; Number of LABs  (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 2                           ;
; 8                                           ; 1                           ;
; 9                                           ; 1                           ;
; 10                                          ; 3                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 4.38) ; Number of LABs  (Total = 8) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 1                           ;
; 1                                               ; 2                           ;
; 2                                               ; 1                           ;
; 3                                               ; 0                           ;
; 4                                               ; 0                           ;
; 5                                               ; 1                           ;
; 6                                               ; 0                           ;
; 7                                               ; 0                           ;
; 8                                               ; 1                           ;
; 9                                               ; 2                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 5.25) ; Number of LABs  (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 2                           ;
; 3                                           ; 0                           ;
; 4                                           ; 2                           ;
; 5                                           ; 0                           ;
; 6                                           ; 1                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 0                           ;
; 11                                          ; 1                           ;
; 12                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Sun Nov 19 23:21:31 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off verilog_seg7 -c verilog_seg7
Info: Selected device EPM1270T144C5 for design "verilog_seg7"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
    Info: Device EPM1270T144C5ES is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[23]" to use Global clock
    Info: Destination "lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella23" may be