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📄 verilog_seg7.fit.rpt

📁 Verilog 经典实例
💻 RPT
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; 3.3-V PCI                  ; 10 pF ; 25 Ohm (Parallel)      ;
+----------------------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity                                                                                                                                                                                                                                                       ;
+-------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                                                        ;
+-------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------+
; |verilog_seg7                             ; 62 (0)      ; 43           ; 0          ; 13   ; 0            ; 19 (0)       ; 0 (0)             ; 43 (0)           ; 41 (0)          ; 0 (0)      ; |verilog_seg7                                                                              ;
;    |addcont:inst|                         ; 8 (8)       ; 8            ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; 0 (0)      ; |verilog_seg7|addcont:inst                                                                 ;
;    |bin27seg:inst6|                       ; 7 (7)       ; 0            ; 0          ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |verilog_seg7|bin27seg:inst6                                                               ;
;    |lpm_counter0:inst4|                   ; 25 (0)      ; 25           ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 25 (0)           ; 25 (0)          ; 0 (0)      ; |verilog_seg7|lpm_counter0:inst4                                                           ;
;       |lpm_counter:lpm_counter_component| ; 25 (0)      ; 25           ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 25 (0)           ; 25 (0)          ; 0 (0)      ; |verilog_seg7|lpm_counter0:inst4|lpm_counter:lpm_counter_component                         ;
;          |cntr_mad:auto_generated|        ; 25 (25)     ; 25           ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 25 (25)          ; 25 (25)         ; 0 (0)      ; |verilog_seg7|lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated ;
;    |segmain:inst1|                        ; 14 (14)     ; 2            ; 0          ; 0    ; 0            ; 12 (12)      ; 0 (0)             ; 2 (2)            ; 0 (0)           ; 0 (0)      ; |verilog_seg7|segmain:inst1                                                                ;
;    |subcont:inst5|                        ; 8 (8)       ; 8            ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; 0 (0)      ; |verilog_seg7|subcont:inst5                                                                ;
+-------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------+
; Delay Chain Summary                  ;
+-----------+----------+---------------+
; Name      ; Pin Type ; Pad to Core 0 ;
+-----------+----------+---------------+
; reset     ; Input    ; 1             ;
; clk       ; Input    ; 0             ;
; ledcom[3] ; Output   ; --            ;
; ledcom[2] ; Output   ; --            ;
; ledcom[1] ; Output   ; --            ;
; ledcom[0] ; Output   ; --            ;
; seg7[6]   ; Output   ; --            ;
; seg7[5]   ; Output   ; --            ;
; seg7[4]   ; Output   ; --            ;
; seg7[3]   ; Output   ; --            ;
; seg7[2]   ; Output   ; --            ;
; seg7[1]   ; Output   ; --            ;
; seg7[0]   ; Output   ; --            ;
+-----------+----------+---------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Control Signals                                                                                                                                                                    ;
+-----------------------------------------------------------------------------------------+--------------+---------+--------------+--------+----------------------+------------------+
; Name                                                                                    ; Location     ; Fan-Out ; Usage        ; Global ; Global Resource Used ; Global Line Name ;
+-----------------------------------------------------------------------------------------+--------------+---------+--------------+--------+----------------------+------------------+
; clk                                                                                     ; PIN_18       ; 25      ; Clock        ; yes    ; Global clock         ; GCLK0            ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[23] ; LC_X14_Y3_N6 ; 9       ; Clock        ; yes    ; Global clock         ; GCLK1            ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[24] ; LC_X14_Y3_N7 ; 9       ; Clock        ; yes    ; Global clock         ; GCLK3            ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[5]  ; LC_X12_Y3_N8 ; 3       ; Clock        ; yes    ; Global clock         ; GCLK2            ;
; reset                                                                                   ; PIN_93       ; 18      ; Async. clear ; no     ; --                   ; --               ;
+-----------------------------------------------------------------------------------------+--------------+---------+--------------+--------+----------------------+------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Global & Other Fast Signals                                                                                                                                ;
+-----------------------------------------------------------------------------------------+--------------+---------+----------------------+------------------+
; Name                                                                                    ; Location     ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-----------------------------------------------------------------------------------------+--------------+---------+----------------------+------------------+
; clk                                                                                     ; PIN_18       ; 25      ; Global clock         ; GCLK0            ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[23] ; LC_X14_Y3_N6 ; 9       ; Global clock         ; GCLK1            ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[24] ; LC_X14_Y3_N7 ; 9       ; Global clock         ; GCLK3            ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[5]  ; LC_X12_Y3_N8 ; 3       ; Global clock         ; GCLK2            ;
+-----------------------------------------------------------------------------------------+--------------+---------+----------------------+------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals                                                                                    ;
+----------------------------------------------------------------------------------------------------------+---------+
; Name                                                                                                     ; Fan-Out ;
+----------------------------------------------------------------------------------------------------------+---------+
; reset                                                                                                    ; 18      ;
; segmain:inst1|comclk[0]                                                                                  ; 13      ;
; segmain:inst1|comclk[1]                                                                                  ; 10      ;
; segmain:inst1|dataout[3]~77                                                                              ; 7       ;
; segmain:inst1|dataout[2]~75                                                                              ; 7       ;
; segmain:inst1|dataout[1]~73                                                                              ; 7       ;
; segmain:inst1|dataout[0]~71                                                                              ; 7       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella6~COUT         ; 5       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella11~COUT        ; 5       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella16~COUT        ; 5       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella1~COUT         ; 5       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella21~COUT        ; 3       ;
; subcont:inst5|cont[4]~57                                                                                 ; 3       ;
; addcont:inst|cont[4]~61                                                                                  ; 3       ;
; subcont:inst5|cont[3]                                                                                    ; 2       ;
; subcont:inst5|cont[7]                                                                                    ; 2       ;
; addcont:inst|cont[7]                                                                                     ; 2       ;
; addcont:inst|cont[3]                                                                                     ; 2       ;
; subcont:inst5|cont[2]                                                                                    ; 2       ;
; addcont:inst|cont[2]                                                                                     ; 2       ;
; addcont:inst|cont[6]                                                                                     ; 2       ;
; subcont:inst5|cont[6]                                                                                    ; 2       ;
; subcont:inst5|cont[1]                                                                                    ; 2       ;
; subcont:inst5|cont[5]                                                                                    ; 2       ;
; addcont:inst|cont[5]                                                                                     ; 2       ;
; addcont:inst|cont[1]                                                                                     ; 2       ;
; subcont:inst5|cont[0]                                                                                    ; 2       ;
; subcont:inst5|cont[4]                                                                                    ; 2       ;
; addcont:inst|cont[4]                                                                                     ; 2       ;
; addcont:inst|cont[0]                                                                                     ; 2       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[6]                   ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella7~COUTCOUT1_3  ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella7~COUT         ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[7]                   ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella8~COUTCOUT1_3  ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella8~COUT         ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[8]                   ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella9~COUTCOUT1_3  ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella9~COUT         ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[9]                   ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella10~COUTCOUT1_3 ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella10~COUT        ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[10]                  ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[11]                  ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella12~COUTCOUT1_3 ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella12~COUT        ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[12]                  ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella13~COUTCOUT1_3 ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella13~COUT        ; 1       ;
; lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[13]                  ; 1       ;
+----------------------------------------------------------------------------------------------------------+---------+


+---------------------------------------------------+
; Interconnect Usage Summary                        ;

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