verilog_seg7.fit.qmsg

Verilog 经典实例

{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0 0 "Moving registers into LUTs to improve timing and density" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0 0 "Finished moving registers into LUTs" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.493 ns register pin " "Info: Estimated most critical path is register to pin delay of 9.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns addcont:inst\|cont\[4\] 1 REG LAB_X9_Y10 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y10; Fanout = 3; REG Node = 'addcont:inst\|cont\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "" { addcont:inst|cont[4] } "NODE_NAME" } "" } } { "addcont.v" "" { Text "D:/verilog_seg7/addcont.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.008 ns) + CELL(0.511 ns) 2.519 ns segmain:inst1\|dataout\[0\]~70 2 COMB LAB_X11_Y10 1 " "Info: 2: + IC(2.008 ns) + CELL(0.511 ns) = 2.519 ns; Loc. = LAB_X11_Y10; Fanout = 1; COMB Node = 'segmain:inst1\|dataout\[0\]~70'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "2.519 ns" { addcont:inst|cont[4] segmain:inst1|dataout[0]~70 } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.672 ns) + CELL(0.511 ns) 3.702 ns segmain:inst1\|dataout\[0\]~71 3 COMB LAB_X11_Y10 7 " "Info: 3: + IC(0.672 ns) + CELL(0.511 ns) = 3.702 ns; Loc. = LAB_X11_Y10; Fanout = 7; COMB Node = 'segmain:inst1\|dataout\[0\]~71'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "1.183 ns" { segmain:inst1|dataout[0]~70 segmain:inst1|dataout[0]~71 } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.750 ns) + CELL(0.914 ns) 5.366 ns bin27seg:inst6\|data_out\[0\]~78 4 COMB LAB_X10_Y10 1 " "Info: 4: + IC(0.750 ns) + CELL(0.914 ns) = 5.366 ns; Loc. = LAB_X10_Y10; Fanout = 1; COMB Node = 'bin27seg:inst6\|data_out\[0\]~78'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "1.664 ns" { segmain:inst1|dataout[0]~71 bin27seg:inst6|data_out[0]~78 } "NODE_NAME" } "" } } { "bin27seg.v" "" { Text "D:/verilog_seg7/bin27seg.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.805 ns) + CELL(2.322 ns) 9.493 ns seg7\[0\] 5 PIN PIN_123 0 " "Info: 5: + IC(1.805 ns) + CELL(2.322 ns) = 9.493 ns; Loc. = PIN_123; Fanout = 0; PIN Node = 'seg7\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "4.127 ns" { bin27seg:inst6|data_out[0]~78 seg7[0] } "NODE_NAME" } "" } } { "verilog_seg7.bdf" "" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 264 728 904 280 "seg7\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.258 ns ( 44.85 % ) " "Info: Total cell delay = 4.258 ns ( 44.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.235 ns ( 55.15 % ) " "Info: Total interconnect delay = 5.235 ns ( 55.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "9.493 ns" { addcont:inst|cont[4] segmain:inst1|dataout[0]~70 segmain:inst1|dataout[0]~71 bin27seg:inst6|data_out[0]~78 seg7[0] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." {  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 19 23:21:41 2006 " "Info: Processing ended: Sun Nov 19 23:21:41 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}