verilog_seg7.tan.qmsg

Verilog 经典实例

{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg7\[3\] segmain:inst1\|comclk\[0\] 18.586 ns register " "Info: tco from clock \"clk\" to destination pin \"seg7\[3\]\" through register \"segmain:inst1\|comclk\[0\]\" is 18.586 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.141 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "" { clk } "NODE_NAME" } "" } } { "verilog_seg7.bdf" "" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 48 288 456 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[5\] 2 REG LC_X12_Y3_N8 5 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N8; Fanout = 5; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "3.032 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[5] } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 8.141 ns segmain:inst1\|comclk\[0\] 3 REG LC_X10_Y10_N0 13 " "Info: 3: + IC(3.028 ns) + CELL(0.918 ns) = 8.141 ns; Loc. = LC_X10_Y10_N0; Fanout = 13; REG Node = 'segmain:inst1\|comclk\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "3.946 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[5] segmain:inst1|comclk[0] } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.46 % ) " "Info: Total cell delay = 3.375 ns ( 41.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.766 ns ( 58.54 % ) " "Info: Total interconnect delay = 4.766 ns ( 58.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "8.141 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[5] segmain:inst1|comclk[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.141 ns" { clk clk~combout lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[5] segmain:inst1|comclk[0] } { 0.000ns 0.000ns 1.738ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.069 ns + Longest register pin " "Info: + Longest register to pin delay is 10.069 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns segmain:inst1\|comclk\[0\] 1 REG LC_X10_Y10_N0 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N0; Fanout = 13; REG Node = 'segmain:inst1\|comclk\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "" { segmain:inst1|comclk[0] } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.914 ns) 2.236 ns segmain:inst1\|dataout\[2\]~74 2 COMB LC_X9_Y10_N9 1 " "Info: 2: + IC(1.322 ns) + CELL(0.914 ns) = 2.236 ns; Loc. = LC_X9_Y10_N9; Fanout = 1; COMB Node = 'segmain:inst1\|dataout\[2\]~74'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "2.236 ns" { segmain:inst1|comclk[0] segmain:inst1|dataout[2]~74 } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.181 ns) + CELL(0.511 ns) 3.928 ns segmain:inst1\|dataout\[2\]~75 3 COMB LC_X10_Y10_N6 7 " "Info: 3: + IC(1.181 ns) + CELL(0.511 ns) = 3.928 ns; Loc. = LC_X10_Y10_N6; Fanout = 7; COMB Node = 'segmain:inst1\|dataout\[2\]~75'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "1.692 ns" { segmain:inst1|dataout[2]~74 segmain:inst1|dataout[2]~75 } "NODE_NAME" } "" } } { "segmain.v" "" { Text "D:/verilog_seg7/segmain.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.857 ns) + CELL(0.200 ns) 5.985 ns bin27seg:inst6\|data_out\[3\]~75 4 COMB LC_X12_Y10_N8 1 " "Info: 4: + IC(1.857 ns) + CELL(0.200 ns) = 5.985 ns; Loc. = LC_X12_Y10_N8; Fanout = 1; COMB Node = 'bin27seg:inst6\|data_out\[3\]~75'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "2.057 ns" { segmain:inst1|dataout[2]~75 bin27seg:inst6|data_out[3]~75 } "NODE_NAME" } "" } } { "bin27seg.v" "" { Text "D:/verilog_seg7/bin27seg.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.762 ns) + CELL(2.322 ns) 10.069 ns seg7\[3\] 5 PIN PIN_114 0 " "Info: 5: + IC(1.762 ns) + CELL(2.322 ns) = 10.069 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'seg7\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "4.084 ns" { bin27seg:inst6|data_out[3]~75 seg7[3] } "NODE_NAME" } "" } } { "verilog_seg7.bdf" "" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 264 728 904 280 "seg7\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.947 ns ( 39.20 % ) " "Info: Total cell delay = 3.947 ns ( 39.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.122 ns ( 60.80 % ) " "Info: Total interconnect delay = 6.122 ns ( 60.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "10.069 ns" { segmain:inst1|comclk[0] segmain:inst1|dataout[2]~74 segmain:inst1|dataout[2]~75 bin27seg:inst6|data_out[3]~75 seg7[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.069 ns" { segmain:inst1|comclk[0] segmain:inst1|dataout[2]~74 segmain:inst1|dataout[2]~75 bin27seg:inst6|data_out[3]~75 seg7[3] } { 0.000ns 1.322ns 1.181ns 1.857ns 1.762ns } { 0.000ns 0.914ns 0.511ns 0.200ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "8.141 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[5] segmain:inst1|comclk[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.141 ns" { clk clk~combout lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[5] segmain:inst1|comclk[0] } { 0.000ns 0.000ns 1.738ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "10.069 ns" { segmain:inst1|comclk[0] segmain:inst1|dataout[2]~74 segmain:inst1|dataout[2]~75 bin27seg:inst6|data_out[3]~75 seg7[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.069 ns" { segmain:inst1|comclk[0] segmain:inst1|dataout[2]~74 segmain:inst1|dataout[2]~75 bin27seg:inst6|data_out[3]~75 seg7[3] } { 0.000ns 1.322ns 1.181ns 1.857ns 1.762ns } { 0.000ns 0.914ns 0.511ns 0.200ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 19 23:21:52 2006 " "Info: Processing ended: Sun Nov 19 23:21:52 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}