verilog_seg7.tan.qmsg

Verilog 经典实例

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "verilog_seg7.bdf" "" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 48 288 456 64 "clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[24\] " "Info: Detected ripple clock \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[24\]\" as buffer" {  } { { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 242 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[24\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[23\] " "Info: Detected ripple clock \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[23\]\" as buffer" {  } { { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 242 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[23\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[5\] " "Info: Detected ripple clock \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[5\]\" as buffer" {  } { { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 242 8 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[2\] register lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[17\] 179.6 MHz 5.568 ns Internal " "Info: Clock \"clk\" has Internal fmax of 179.6 MHz between source register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[2\]\" and destination register \"lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[17\]\" (period= 5.568 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.859 ns + Longest register register " "Info: + Longest register to register delay is 4.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[2\] 1 REG LC_X12_Y3_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y3_N5; Fanout = 3; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.978 ns) 1.870 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella2~COUT 2 COMB LC_X12_Y3_N5 2 " "Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X12_Y3_N5; Fanout = 2; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella2~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "1.870 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella2~COUT } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 1.993 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella3~COUT 3 COMB LC_X12_Y3_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X12_Y3_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella3~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "0.123 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella2~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella3~COUT } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 54 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.116 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella4~COUT 4 COMB LC_X12_Y3_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X12_Y3_N7; Fanout = 2; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella4~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "0.123 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella3~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella4~COUT } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 62 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.239 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella5~COUT 5 COMB LC_X12_Y3_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X12_Y3_N8; Fanout = 2; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella5~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "0.123 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella4~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella5~COUT } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 70 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 2.638 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella6~COUT 6 COMB LC_X12_Y3_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X12_Y3_N9; Fanout = 6; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella6~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "0.399 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella5~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella6~COUT } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 78 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.246 ns) 2.884 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella11~COUT 7 COMB LC_X13_Y3_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.246 ns) = 2.884 ns; Loc. = LC_X13_Y3_N4; Fanout = 6; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella11~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "0.246 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella6~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella11~COUT } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 118 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.349 ns) 3.233 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella16~COUT 8 COMB LC_X13_Y3_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.349 ns) = 3.233 ns; Loc. = LC_X13_Y3_N9; Fanout = 6; COMB Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|counter_cella16~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "0.349 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella11~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella16~COUT } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 158 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.626 ns) 4.859 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[17\] 9 REG LC_X14_Y3_N0 3 " "Info: 9: + IC(0.000 ns) + CELL(1.626 ns) = 4.859 ns; Loc. = LC_X14_Y3_N0; Fanout = 3; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[17\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "1.626 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella16~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.967 ns ( 81.64 % ) " "Info: Total cell delay = 3.967 ns ( 81.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.892 ns ( 18.36 % ) " "Info: Total interconnect delay = 0.892 ns ( 18.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "4.859 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella2~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella3~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella4~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella5~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella6~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella11~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella16~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.859 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella2~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella3~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella4~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella5~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella6~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella11~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella16~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } { 0.000ns 0.892ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 0.246ns 0.349ns 1.626ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "" { clk } "NODE_NAME" } "" } } { "verilog_seg7.bdf" "" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 48 288 456 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[17\] 2 REG LC_X14_Y3_N0 3 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X14_Y3_N0; Fanout = 3; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[17\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "2.656 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "3.819 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "" { clk } "NODE_NAME" } "" } } { "verilog_seg7.bdf" "" { Schematic "D:/verilog_seg7/verilog_seg7.bdf" { { 48 288 456 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[2\] 2 REG LC_X12_Y3_N5 3 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X12_Y3_N5; Fanout = 3; REG Node = 'lpm_counter0:inst4\|lpm_counter:lpm_counter_component\|cntr_mad:auto_generated\|safe_q\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "2.656 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "3.819 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "3.819 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "3.819 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 242 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "db/cntr_mad.tdf" "" { Text "D:/verilog_seg7/db/cntr_mad.tdf" 242 8 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "4.859 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella2~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella3~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella4~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella5~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella6~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella11~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella16~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.859 ns" { lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella2~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella3~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella4~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella5~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella6~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella11~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella16~COUT lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } { 0.000ns 0.892ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 0.246ns 0.349ns 1.626ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "3.819 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[17] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "verilog_seg7" "UNKNOWN" "V1" "D:/verilog_seg7/db/verilog_seg7.quartus_db" { Floorplan "D:/verilog_seg7/" "" "3.819 ns" { clk lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[2] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}