verilog_seg7.map.eqn

Verilog 经典实例

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--C1_comclk[1] is segmain:inst1|comclk[1]
--operation mode is normal

C1_comclk[1]_lut_out = C1_comclk[1] $ C1_comclk[0];
C1_comclk[1] = DFFEAS(C1_comclk[1]_lut_out, H1_safe_q[5], reset, , , , , , );


--C1_comclk[0] is segmain:inst1|comclk[0]
--operation mode is normal

C1_comclk[0]_lut_out = !C1_comclk[0];
C1_comclk[0] = DFFEAS(C1_comclk[0]_lut_out, H1_safe_q[5], reset, , , , , , );


--C1L15 is segmain:inst1|ledcom[3]~41
--operation mode is normal

C1L15 = !C1_comclk[0] # !C1_comclk[1];


--C1L1 is segmain:inst1|Equal~58
--operation mode is normal

C1L1 = C1_comclk[1] & (!C1_comclk[0]);


--C1L2 is segmain:inst1|Equal~59
--operation mode is normal

C1L2 = C1_comclk[0] & (!C1_comclk[1]);


--C1L14 is segmain:inst1|ledcom[0]~42
--operation mode is normal

C1L14 = C1_comclk[1] # C1_comclk[0];


--B1_cont[0] is addcont:inst|cont[0]
--operation mode is arithmetic

B1_cont[0]_lut_out = !B1_cont[0];
B1_cont[0] = DFFEAS(B1_cont[0]_lut_out, H1_safe_q[23], reset, , , , , , );

--B1L3 is addcont:inst|cont[0]~57
--operation mode is arithmetic

B1L3 = CARRY(B1_cont[0]);


--B1_cont[4] is addcont:inst|cont[4]
--operation mode is arithmetic

B1_cont[4]_carry_eqn = B1L9;
B1_cont[4]_lut_out = B1_cont[4] $ (!B1_cont[4]_carry_eqn);
B1_cont[4] = DFFEAS(B1_cont[4]_lut_out, H1_safe_q[23], reset, , , , , , );

--B1L11 is addcont:inst|cont[4]~61
--operation mode is arithmetic

B1L11 = CARRY(B1_cont[4] & (!B1L9));


--E1_cont[4] is subcont:inst5|cont[4]
--operation mode is arithmetic

E1_cont[4]_carry_eqn = E1L9;
E1_cont[4]_lut_out = E1_cont[4] $ (E1_cont[4]_carry_eqn);
E1_cont[4] = DFFEAS(E1_cont[4]_lut_out, H1_safe_q[24], reset, , , , , , );

--E1L11 is subcont:inst5|cont[4]~57
--operation mode is arithmetic

E1L11 = CARRY(E1_cont[4] # !E1L9);


--C1L6 is segmain:inst1|dataout[0]~70
--operation mode is normal

C1L6 = C1_comclk[1] & C1_comclk[0] & B1_cont[4] # !C1_comclk[1] & (E1_cont[4] # !C1_comclk[0]);


--E1_cont[0] is subcont:inst5|cont[0]
--operation mode is arithmetic

E1_cont[0]_lut_out = !E1_cont[0];
E1_cont[0] = DFFEAS(E1_cont[0]_lut_out, H1_safe_q[24], reset, , , , , , );

--E1L3 is subcont:inst5|cont[0]~61
--operation mode is arithmetic

E1L3 = CARRY(E1_cont[0]);


--C1L7 is segmain:inst1|dataout[0]~71
--operation mode is normal

C1L7 = C1_comclk[0] & (C1L6) # !C1_comclk[0] & (C1L6 & (E1_cont[0]) # !C1L6 & B1_cont[0]);


--B1_cont[1] is addcont:inst|cont[1]
--operation mode is arithmetic

B1_cont[1]_carry_eqn = B1L3;
B1_cont[1]_lut_out = B1_cont[1] $ (B1_cont[1]_carry_eqn);
B1_cont[1] = DFFEAS(B1_cont[1]_lut_out, H1_safe_q[23], reset, , , , , , );

--B1L5 is addcont:inst|cont[1]~65
--operation mode is arithmetic

B1L5 = CARRY(!B1L3 # !B1_cont[1]);


--B1_cont[5] is addcont:inst|cont[5]
--operation mode is arithmetic

B1_cont[5]_carry_eqn = B1L11;
B1_cont[5]_lut_out = B1_cont[5] $ (B1_cont[5]_carry_eqn);
B1_cont[5] = DFFEAS(B1_cont[5]_lut_out, H1_safe_q[23], reset, , , , , , );

--B1L13 is addcont:inst|cont[5]~69
--operation mode is arithmetic

B1L13 = CARRY(!B1L11 # !B1_cont[5]);


--E1_cont[5] is subcont:inst5|cont[5]
--operation mode is arithmetic

E1_cont[5]_carry_eqn = E1L11;
E1_cont[5]_lut_out = E1_cont[5] $ (!E1_cont[5]_carry_eqn);
E1_cont[5] = DFFEAS(E1_cont[5]_lut_out, H1_safe_q[24], reset, , , , , , );

--E1L13 is subcont:inst5|cont[5]~65
--operation mode is arithmetic

E1L13 = CARRY(!E1_cont[5] & (!E1L11));


--C1L8 is segmain:inst1|dataout[1]~72
--operation mode is normal

C1L8 = C1_comclk[1] & C1_comclk[0] & B1_cont[5] # !C1_comclk[1] & (E1_cont[5] # !C1_comclk[0]);


--E1_cont[1] is subcont:inst5|cont[1]
--operation mode is arithmetic

E1_cont[1]_carry_eqn = E1L3;
E1_cont[1]_lut_out = E1_cont[1] $ (!E1_cont[1]_carry_eqn);
E1_cont[1] = DFFEAS(E1_cont[1]_lut_out, H1_safe_q[24], reset, , , , , , );

--E1L5 is subcont:inst5|cont[1]~69
--operation mode is arithmetic

E1L5 = CARRY(!E1_cont[1] & (!E1L3));


--C1L9 is segmain:inst1|dataout[1]~73
--operation mode is normal

C1L9 = C1_comclk[0] & (C1L8) # !C1_comclk[0] & (C1L8 & (E1_cont[1]) # !C1L8 & B1_cont[1]);


--E1_cont[6] is subcont:inst5|cont[6]
--operation mode is arithmetic

E1_cont[6]_carry_eqn = E1L13;
E1_cont[6]_lut_out = E1_cont[6] $ (E1_cont[6]_carry_eqn);
E1_cont[6] = DFFEAS(E1_cont[6]_lut_out, H1_safe_q[24], reset, , , , , , );

--E1L15 is subcont:inst5|cont[6]~73
--operation mode is arithmetic

E1L15 = CARRY(E1_cont[6] # !E1L13);


--B1_cont[6] is addcont:inst|cont[6]
--operation mode is arithmetic

B1_cont[6]_carry_eqn = B1L13;
B1_cont[6]_lut_out = B1_cont[6] $ (!B1_cont[6]_carry_eqn);
B1_cont[6] = DFFEAS(B1_cont[6]_lut_out, H1_safe_q[23], reset, , , , , , );

--B1L15 is addcont:inst|cont[6]~73
--operation mode is arithmetic

B1L15 = CARRY(B1_cont[6] & (!B1L13));


--B1_cont[2] is addcont:inst|cont[2]
--operation mode is arithmetic

B1_cont[2]_carry_eqn = B1L5;
B1_cont[2]_lut_out = B1_cont[2] $ (!B1_cont[2]_carry_eqn);
B1_cont[2] = DFFEAS(B1_cont[2]_lut_out, H1_safe_q[23], reset, , , , , , );

--B1L7 is addcont:inst|cont[2]~77
--operation mode is arithmetic

B1L7 = CARRY(B1_cont[2] & (!B1L5));


--C1L10 is segmain:inst1|dataout[2]~74
--operation mode is normal

C1L10 = C1_comclk[1] & (C1_comclk[0] & B1_cont[6] # !C1_comclk[0] & (B1_cont[2])) # !C1_comclk[1] & !C1_comclk[0];


--E1_cont[2] is subcont:inst5|cont[2]
--operation mode is arithmetic

E1_cont[2]_carry_eqn = E1L5;
E1_cont[2]_lut_out = E1_cont[2] $ (E1_cont[2]_carry_eqn);
E1_cont[2] = DFFEAS(E1_cont[2]_lut_out, H1_safe_q[24], reset, , , , , , );

--E1L7 is subcont:inst5|cont[2]~77
--operation mode is arithmetic

E1L7 = CARRY(E1_cont[2] # !E1L5);


--C1L11 is segmain:inst1|dataout[2]~75
--operation mode is normal

C1L11 = C1_comclk[1] & (C1L10) # !C1_comclk[1] & (C1L10 & (E1_cont[2]) # !C1L10 & E1_cont[6]);


--B1_cont[3] is addcont:inst|cont[3]
--operation mode is arithmetic

B1_cont[3]_carry_eqn = B1L7;
B1_cont[3]_lut_out = B1_cont[3] $ (B1_cont[3]_carry_eqn);
B1_cont[3] = DFFEAS(B1_cont[3]_lut_out, H1_safe_q[23], reset, , , , , , );

--B1L9 is addcont:inst|cont[3]~81
--operation mode is arithmetic

B1L9 = CARRY(!B1L7 # !B1_cont[3]);


--B1_cont[7] is addcont:inst|cont[7]
--operation mode is normal

B1_cont[7]_carry_eqn = B1L15;
B1_cont[7]_lut_out = B1_cont[7] $ (B1_cont[7]_carry_eqn);
B1_cont[7] = DFFEAS(B1_cont[7]_lut_out, H1_safe_q[23], reset, , , , , , );


--E1_cont[7] is subcont:inst5|cont[7]
--operation mode is normal

E1_cont[7]_carry_eqn = E1L15;
E1_cont[7]_lut_out = E1_cont[7] $ (!E1_cont[7]_carry_eqn);
E1_cont[7] = DFFEAS(E1_cont[7]_lut_out, H1_safe_q[24], reset, , , , , , );


--C1L12 is segmain:inst1|dataout[3]~76
--operation mode is normal

C1L12 = C1_comclk[1] & C1_comclk[0] & B1_cont[7] # !C1_comclk[1] & (E1_cont[7] # !C1_comclk[0]);


--E1_cont[3] is subcont:inst5|cont[3]
--operation mode is arithmetic

E1_cont[3]_carry_eqn = E1L7;
E1_cont[3]_lut_out = E1_cont[3] $ (!E1_cont[3]_carry_eqn);
E1_cont[3] = DFFEAS(E1_cont[3]_lut_out, H1_safe_q[24], reset, , , , , , );

--E1L9 is subcont:inst5|cont[3]~85
--operation mode is arithmetic

E1L9 = CARRY(!E1_cont[3] & (!E1L7));


--C1L13 is segmain:inst1|dataout[3]~77
--operation mode is normal

C1L13 = C1_comclk[0] & (C1L12) # !C1_comclk[0] & (C1L12 & (E1_cont[3]) # !C1L12 & B1_cont[3]);


--F1L7 is bin27seg:inst6|data_out[6]~72
--operation mode is normal

F1L7 = C1L13 # C1L9 & (!C1L11 # !C1L7) # !C1L9 & (C1L11);


--F1L6 is bin27seg:inst6|data_out[5]~73
--operation mode is normal

F1L6 = C1L9 & !C1L13 & (C1L7 # !C1L11) # !C1L9 & (C1L11 & (C1L13) # !C1L11 & C1L7 & !C1L13);


--F1L5 is bin27seg:inst6|data_out[4]~74
--operation mode is normal

F1L5 = C1L9 & C1L7 & (!C1L13) # !C1L9 & (C1L11 & (!C1L13) # !C1L11 & C1L7);


--F1L4 is bin27seg:inst6|data_out[3]~75
--operation mode is normal

F1L4 = C1L7 & (C1L9 $ !C1L11) # !C1L7 & (C1L9 & !C1L11 & C1L13 # !C1L9 & C1L11 & !C1L13);


--F1L3 is bin27seg:inst6|data_out[2]~76
--operation mode is normal

F1L3 = C1L11 & C1L13 & (C1L9 # !C1L7) # !C1L11 & !C1L7 & C1L9 & !C1L13;


--F1L2 is bin27seg:inst6|data_out[1]~77
--operation mode is normal

F1L2 = C1L9 & (C1L7 & (C1L13) # !C1L7 & C1L11) # !C1L9 & C1L11 & (C1L7 $ C1L13);


--F1L1 is bin27seg:inst6|data_out[0]~78
--operation mode is normal

F1L1 = C1L11 & (C1L13 & (!C1L9) # !C1L13 & !C1L7) # !C1L11 & C1L7 & (C1L9 $ !C1L13);


--H1_safe_q[5] is lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[5]
--operation mode is arithmetic

H1_safe_q[5]_carry_eqn = H1L10;
H1_safe_q[5]_lut_out = H1_safe_q[5] $ (H1_safe_q[5]_carry_eqn);
H1_safe_q[5] = DFFEAS(H1_safe_q[5]_lut_out, clk, VCC, , , , , , );

--H1L12 is lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella5~COUT
--operation mode is arithmetic

H1L12 = CARRY(!H1L10 # !H1_safe_q[5]);


--H1_safe_q[23] is lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[23]
--operation mode is arithmetic

H1_safe_q[23]_carry_eqn = H1L46;
H1_safe_q[23]_lut_out = H1_safe_q[23] $ (H1_safe_q[23]_carry_eqn);
H1_safe_q[23] = DFFEAS(H1_safe_q[23]_lut_out, clk, VCC, , , , , , );

--H1L48 is lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|counter_cella23~COUT
--operation mode is arithmetic

H1L48 = CARRY(!H1L46 # !H1_safe_q[23]);


--H1_safe_q[24] is lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated|safe_q[24]
--operation mode is normal

H1_safe_q[24]_carry_eqn = H1L48;
H1_safe_q[24]_lut_out = H1_safe_q[24] $ (!H1_safe_q[24]_carry_eqn);