📄 verilog_seg7.map.rpt
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; -- 4 input functions ; 15 ;
; -- 3 input functions ; 0 ;
; -- 2 input functions ; 43 ;
; -- 1 input functions ; 4 ;
; -- 0 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 24 ;
; -- arithmetic mode ; 38 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 18 ;
; ; ;
; Total registers ; 43 ;
; Total logic cells in carry chains ; 41 ;
; I/O pins ; 13 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 25 ;
; Total fan-out ; 222 ;
; Average fan-out ; 2.96 ;
+---------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------+
; |verilog_seg7 ; 62 (0) ; 43 ; 0 ; 13 ; 0 ; 19 (0) ; 0 (0) ; 43 (0) ; 41 (0) ; 0 (0) ; |verilog_seg7 ;
; |addcont:inst| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; 0 (0) ; |verilog_seg7|addcont:inst ;
; |bin27seg:inst6| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |verilog_seg7|bin27seg:inst6 ;
; |lpm_counter0:inst4| ; 25 (0) ; 25 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 25 (0) ; 25 (0) ; 0 (0) ; |verilog_seg7|lpm_counter0:inst4 ;
; |lpm_counter:lpm_counter_component| ; 25 (0) ; 25 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 25 (0) ; 25 (0) ; 0 (0) ; |verilog_seg7|lpm_counter0:inst4|lpm_counter:lpm_counter_component ;
; |cntr_mad:auto_generated| ; 25 (25) ; 25 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 25 (25) ; 25 (25) ; 0 (0) ; |verilog_seg7|lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated ;
; |segmain:inst1| ; 14 (14) ; 2 ; 0 ; 0 ; 0 ; 12 (12) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |verilog_seg7|segmain:inst1 ;
; |subcont:inst5| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; 0 (0) ; |verilog_seg7|subcont:inst5 ;
+-------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 43 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 18 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |verilog_seg7|segmain:inst1|ledcom[3] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |verilog_seg7|segmain:inst1|dataout[3] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_counter0:inst4|lpm_counter:lpm_counter_component ;
+------------------------+-------------+------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+------------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 26 ; Integer ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ;
; DEVICE_FAMILY ; MAX II ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; cntr_mad ; Untyped ;
+------------------------+-------------+------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/verilog_seg7/verilog_seg7.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Sun Nov 19 23:21:17 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off verilog_seg7 -c verilog_seg7
Info: Assignment "TCL_SCRIPT_FILE" is no longer supported -- removing assignment from Quartus II Settings File
Info: Found 1 design units, including 1 entities, in source file verilog_seg7.bdf
Info: Found entity 1: verilog_seg7
Info: Elaborating entity "verilog_seg7" for the top level hierarchy
Warning: Using design file segmain.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: segmain
Info: Elaborating entity "segmain" for hierarchy "segmain:inst1"
Warning (10230): Verilog HDL assignment warning at segmain.v(29): truncated value with size 32 to match size of target (2)
Warning (10235): Verilog HDL Always Construct warning at segmain.v(44): variable "datain" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at segmain.v(45): variable "datain" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at segmain.v(46): variable "datain" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at segmain.v(47): variable "datain" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Using design file lpm_counter0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: lpm_counter0-SYN
Info: Found entity 1: lpm_counter0
Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst4"
Info: Found 1 design units, including 1 entities, in source file ../altera/quartus51/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst4|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_mad.tdf
Info: Found entity 1: cntr_mad
Info: Elaborating entity "cntr_mad" for hierarchy "lpm_counter0:inst4|lpm_counter:lpm_counter_component|cntr_mad:auto_generated"
Warning: Using design file subcont.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: subcont
Info: Elaborating entity "subcont" for hierarchy "subcont:inst5"
Warning (10230): Verilog HDL assignment warning at subcont.v(16): truncated value with size 32 to match size of target (8)
Warning: Using design file addcont.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: addcont
Info: Elaborating entity "addcont" for hierarchy "addcont:inst"
Warning (10230): Verilog HDL assignment warning at addcont.v(16): truncated value with size 32 to match size of target (8)
Warning: Using design file bin27seg.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: bin27seg
Info: Elaborating entity "bin27seg" for hierarchy "bin27seg:inst6"
Info: Implemented 75 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 11 output pins
Info: Implemented 62 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Processing ended: Sun Nov 19 23:21:26 2006
Info: Elapsed time: 00:00:10
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