seg7led.map.rpt

Verilog 经典实例

+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_counter0:inst|lpm_counter:lpm_counter_component ;
+------------------------+-------------+-----------------------------------------------------------+
; Parameter Name         ; Value       ; Type                                                      ;
+------------------------+-------------+-----------------------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                                                ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                              ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                              ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                                            ;
; LPM_WIDTH              ; 16          ; Signed Integer                                            ;
; LPM_DIRECTION          ; UP          ; Untyped                                                   ;
; LPM_MODULUS            ; 0           ; Untyped                                                   ;
; LPM_AVALUE             ; UNUSED      ; Untyped                                                   ;
; LPM_SVALUE             ; UNUSED      ; Untyped                                                   ;
; LPM_PORT_UPDOWN        ; PORT_UNUSED ; Untyped                                                   ;
; DEVICE_FAMILY          ; Cyclone     ; Untyped                                                   ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                                                   ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH                                        ;
; NOT_GATE_PUSH_BACK     ; ON          ; NOT_GATE_PUSH_BACK                                        ;
; CARRY_CNT_EN           ; SMART       ; Untyped                                                   ;
; LABWIDE_SCLR           ; ON          ; Untyped                                                   ;
; USE_NEW_VERSION        ; TRUE        ; Untyped                                                   ;
; CBXI_PARAMETER         ; cntr_dth    ; Untyped                                                   ;
+------------------------+-------------+-----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: int_div:inst6          ;
+----------------+----------------------------------+-----------------+
; Parameter Name ; Value                            ; Type            ;
+----------------+----------------------------------+-----------------+
; CLK_FREQ       ; 00000010111110101111000010000000 ; Unsigned Binary ;
; DCLK_FREQ      ; 00000000000000000000000000001010 ; Unsigned Binary ;
+----------------+----------------------------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Dec 28 21:56:38 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seg7led -c seg7led
Warning: Ignored assignments for entity "seg7led" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" is ignored
    Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" is ignored
    Warning: Assignment of entity set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -section_id Top is ignored
Info: Found 1 design units, including 1 entities, in source file seg7led.bdf
    Info: Found entity 1: seg7led
Info: Found 1 design units, including 1 entities, in source file segmain.v
    Info: Found entity 1: segmain
Info: Found 1 design units, including 1 entities, in source file int_div.v
    Info: Found entity 1: int_div
Info: Elaborating entity "seg7led" for the top level hierarchy
Warning: Block or symbol "lpm_counter0" of instance "inst" overlaps another block or symbol
Info: Elaborating entity "segmain" for hierarchy "segmain:inst1"
Warning: Using design file lpm_counter0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lpm_counter0
Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "lpm_counter0:inst|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_dth.tdf
    Info: Found entity 1: cntr_dth
Info: Elaborating entity "cntr_dth" for hierarchy "lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated"
Info: Elaborating entity "int_div" for hierarchy "int_div:inst6"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "78leddata[7]" stuck at VCC
Info: 22 registers lost all their fanouts during netlist optimizations. The first 22 are displayed below.
    Info: Register "segmain:inst1|count[15]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[16]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[17]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[18]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[19]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[20]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[21]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[22]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[23]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[24]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[25]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[26]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[27]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[28]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[29]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[30]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[31]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[32]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[33]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[34]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[35]" lost all its fanouts during netlist optimizations.
    Info: Register "segmain:inst1|count[36]" lost all its fanouts during netlist optimizations.
Info: Generated suppressed messages file G:/Q71/verilog/seg7led/seg7led.map.smsg
Info: Implemented 106 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 12 output pins
    Info: Implemented 92 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
    Info: Allocated 145 megabytes of memory during processing
    Info: Processing ended: Fri Dec 28 21:56:40 2007
    Info: Elapsed time: 00:00:02


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in G:/Q71/verilog/seg7led/seg7led.map.smsg.