prev_cmp_seg7led.fit.qmsg

Verilog 经典实例

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.681 ns register register " "Info: Estimated most critical path is register to register delay of 5.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst5\|clk_div\[8\] 1 REG LAB_X12_Y12 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y12; Fanout = 4; REG Node = 'int_div:inst5\|clk_div\[8\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_div:inst5|clk_div[8] } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(0.114 ns) 1.411 ns int_div:inst5\|LessThan0~562 2 COMB LAB_X12_Y13 1 " "Info: 2: + IC(1.297 ns) + CELL(0.114 ns) = 1.411 ns; Loc. = LAB_X12_Y13; Fanout = 1; COMB Node = 'int_div:inst5\|LessThan0~562'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.411 ns" { int_div:inst5|clk_div[8] int_div:inst5|LessThan0~562 } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.442 ns) 2.776 ns int_div:inst5\|LessThan0~564 3 COMB LAB_X12_Y10 1 " "Info: 3: + IC(0.923 ns) + CELL(0.442 ns) = 2.776 ns; Loc. = LAB_X12_Y10; Fanout = 1; COMB Node = 'int_div:inst5\|LessThan0~564'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.365 ns" { int_div:inst5|LessThan0~562 int_div:inst5|LessThan0~564 } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.211 ns) + CELL(0.442 ns) 3.429 ns int_div:inst5\|LessThan0~565 4 COMB LAB_X12_Y10 33 " "Info: 4: + IC(0.211 ns) + CELL(0.442 ns) = 3.429 ns; Loc. = LAB_X12_Y10; Fanout = 33; COMB Node = 'int_div:inst5\|LessThan0~565'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { int_div:inst5|LessThan0~564 int_div:inst5|LessThan0~565 } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.140 ns) + CELL(1.112 ns) 5.681 ns int_div:inst5\|clk_div\[5\] 5 REG LAB_X12_Y13 3 " "Info: 5: + IC(1.140 ns) + CELL(1.112 ns) = 5.681 ns; Loc. = LAB_X12_Y13; Fanout = 3; REG Node = 'int_div:inst5\|clk_div\[5\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.252 ns" { int_div:inst5|LessThan0~565 int_div:inst5|clk_div[5] } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.110 ns ( 37.14 % ) " "Info: Total cell delay = 2.110 ns ( 37.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.571 ns ( 62.86 % ) " "Info: Total interconnect delay = 3.571 ns ( 62.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.681 ns" { int_div:inst5|clk_div[8] int_div:inst5|LessThan0~562 int_div:inst5|LessThan0~564 int_div:inst5|LessThan0~565 int_div:inst5|clk_div[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X24_Y11 X35_Y21 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X24_Y11 to location X35_Y21" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "78leddata\[7\] VCC " "Info: Pin 78leddata\[7\] has VCC driving its datain port" {  } { { "g:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "g:/altera/72/quartus/bin/pin_planner.ppl" { 78leddata[7] } } } { "g:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "78leddata\[7\]" } } } } { "seg7led.bdf" "" { Schematic "G:/Q71/verilog/seg7led/seg7led.bdf" { { 176 632 808 192 "78leddata\[7..0\]" "" } } } } { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { 78leddata[7] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { 78leddata[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "G:/Q71/verilog/seg7led/seg7led.fit.smsg " "Info: Generated suppressed messages file G:/Q71/verilog/seg7led/seg7led.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "172 " "Info: Allocated 172 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 28 21:55:14 2007 " "Info: Processing ended: Fri Dec 28 21:55:14 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}