seg7led.tan.qmsg

Verilog 经典实例

{ "Info" "ITDB_TH_RESULT" "lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[8\] reset clk -2.465 ns register " "Info: th for register \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[8\]\" (data pin = \"reset\", clock pin = \"clk\") is -2.465 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.326 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.326 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 48 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 48; CLK Node = 'clk'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "G:/Q71/verilog/seg7led/seg7led.bdf" { { 64 -16 152 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.935 ns) 3.178 ns int_div:inst6\|div_out 2 REG LC_X7_Y18_N2 17 " "Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X7_Y18_N2; Fanout = 17; REG Node = 'int_div:inst6\|div_out'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clk int_div:inst6|div_out } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.437 ns) + CELL(0.711 ns) 8.326 ns lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[8\] 3 REG LC_X32_Y6_N0 4 " "Info: 3: + IC(4.437 ns) + CELL(0.711 ns) = 8.326 ns; Loc. = LC_X32_Y6_N0; Fanout = 4; REG Node = 'lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[8\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.148 ns" { int_div:inst6|div_out lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[8] } "NODE_NAME" } } { "db/cntr_dth.tdf" "" { Text "G:/Q71/verilog/seg7led/db/cntr_dth.tdf" 163 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 37.41 % ) " "Info: Total cell delay = 3.115 ns ( 37.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.211 ns ( 62.59 % ) " "Info: Total interconnect delay = 5.211 ns ( 62.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.326 ns" { clk int_div:inst6|div_out lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[8] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.326 ns" { clk {} clk~out0 {} int_div:inst6|div_out {} lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[8] {} } { 0.000ns 0.000ns 0.774ns 4.437ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "db/cntr_dth.tdf" "" { Text "G:/Q71/verilog/seg7led/db/cntr_dth.tdf" 163 8 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.806 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.806 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 PIN PIN_61 31 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_61; Fanout = 31; PIN Node = 'reset'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "G:/Q71/verilog/seg7led/seg7led.bdf" { { 112 -16 152 128 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.219 ns) + CELL(1.112 ns) 10.806 ns lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[8\] 2 REG LC_X32_Y6_N0 4 " "Info: 2: + IC(8.219 ns) + CELL(1.112 ns) = 10.806 ns; Loc. = LC_X32_Y6_N0; Fanout = 4; REG Node = 'lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[8\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.331 ns" { reset lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[8] } "NODE_NAME" } } { "db/cntr_dth.tdf" "" { Text "G:/Q71/verilog/seg7led/db/cntr_dth.tdf" 163 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.587 ns ( 23.94 % ) " "Info: Total cell delay = 2.587 ns ( 23.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.219 ns ( 76.06 % ) " "Info: Total interconnect delay = 8.219 ns ( 76.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.806 ns" { reset lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[8] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.806 ns" { reset {} reset~out0 {} lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[8] {} } { 0.000ns 0.000ns 8.219ns } { 0.000ns 1.475ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.326 ns" { clk int_div:inst6|div_out lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[8] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.326 ns" { clk {} clk~out0 {} int_div:inst6|div_out {} lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[8] {} } { 0.000ns 0.000ns 0.774ns 4.437ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.806 ns" { reset lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[8] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.806 ns" { reset {} reset~out0 {} lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[8] {} } { 0.000ns 0.000ns 8.219ns } { 0.000ns 1.475ns 1.112ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 28 21:56:47 2007 " "Info: Processing ended: Fri Dec 28 21:56:47 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}