seg7led.tan.qmsg

Verilog 经典实例

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "int_div:inst6\|div_out " "Info: Detected ripple clock \"int_div:inst6\|div_out\" as buffer" {  } { { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 4 -1 0 } } { "g:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "int_div:inst6\|div_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register int_div:inst6\|clk_div\[23\] register int_div:inst6\|clk_div\[5\] 161.76 MHz 6.182 ns Internal " "Info: Clock \"clk\" has Internal fmax of 161.76 MHz between source register \"int_div:inst6\|clk_div\[23\]\" and destination register \"int_div:inst6\|clk_div\[5\]\" (period= 6.182 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.921 ns + Longest register register " "Info: + Longest register to register delay is 5.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns int_div:inst6\|clk_div\[23\] 1 REG LC_X7_Y16_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y16_N7; Fanout = 4; REG Node = 'int_div:inst6\|clk_div\[23\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { int_div:inst6|clk_div[23] } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.442 ns) 1.662 ns int_div:inst6\|LessThan0~708 2 COMB LC_X7_Y15_N7 1 " "Info: 2: + IC(1.220 ns) + CELL(0.442 ns) = 1.662 ns; Loc. = LC_X7_Y15_N7; Fanout = 1; COMB Node = 'int_div:inst6\|LessThan0~708'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.662 ns" { int_div:inst6|clk_div[23] int_div:inst6|LessThan0~708 } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.216 ns) + CELL(0.114 ns) 2.992 ns int_div:inst6\|LessThan0~710 3 COMB LC_X6_Y17_N1 1 " "Info: 3: + IC(1.216 ns) + CELL(0.114 ns) = 2.992 ns; Loc. = LC_X6_Y17_N1; Fanout = 1; COMB Node = 'int_div:inst6\|LessThan0~710'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.330 ns" { int_div:inst6|LessThan0~708 int_div:inst6|LessThan0~710 } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.114 ns) 3.528 ns int_div:inst6\|LessThan0~716 4 COMB LC_X6_Y17_N0 33 " "Info: 4: + IC(0.422 ns) + CELL(0.114 ns) = 3.528 ns; Loc. = LC_X6_Y17_N0; Fanout = 33; COMB Node = 'int_div:inst6\|LessThan0~716'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.536 ns" { int_div:inst6|LessThan0~710 int_div:inst6|LessThan0~716 } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.281 ns) + CELL(1.112 ns) 5.921 ns int_div:inst6\|clk_div\[5\] 5 REG LC_X7_Y18_N9 2 " "Info: 5: + IC(1.281 ns) + CELL(1.112 ns) = 5.921 ns; Loc. = LC_X7_Y18_N9; Fanout = 2; REG Node = 'int_div:inst6\|clk_div\[5\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { int_div:inst6|LessThan0~716 int_div:inst6|clk_div[5] } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.782 ns ( 30.10 % ) " "Info: Total cell delay = 1.782 ns ( 30.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.139 ns ( 69.90 % ) " "Info: Total interconnect delay = 4.139 ns ( 69.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.921 ns" { int_div:inst6|clk_div[23] int_div:inst6|LessThan0~708 int_div:inst6|LessThan0~710 int_div:inst6|LessThan0~716 int_div:inst6|clk_div[5] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.921 ns" { int_div:inst6|clk_div[23] {} int_div:inst6|LessThan0~708 {} int_div:inst6|LessThan0~710 {} int_div:inst6|LessThan0~716 {} int_div:inst6|clk_div[5] {} } { 0.000ns 1.220ns 1.216ns 0.422ns 1.281ns } { 0.000ns 0.442ns 0.114ns 0.114ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 48 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 48; CLK Node = 'clk'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "G:/Q71/verilog/seg7led/seg7led.bdf" { { 64 -16 152 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns int_div:inst6\|clk_div\[5\] 2 REG LC_X7_Y18_N9 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y18_N9; Fanout = 2; REG Node = 'int_div:inst6\|clk_div\[5\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk int_div:inst6|clk_div[5] } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk int_div:inst6|clk_div[5] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} int_div:inst6|clk_div[5] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 48 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 48; CLK Node = 'clk'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "G:/Q71/verilog/seg7led/seg7led.bdf" { { 64 -16 152 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns int_div:inst6\|clk_div\[23\] 2 REG LC_X7_Y16_N7 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y16_N7; Fanout = 4; REG Node = 'int_div:inst6\|clk_div\[23\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk int_div:inst6|clk_div[23] } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk int_div:inst6|clk_div[23] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} int_div:inst6|clk_div[23] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk int_div:inst6|clk_div[5] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} int_div:inst6|clk_div[5] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk int_div:inst6|clk_div[23] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} int_div:inst6|clk_div[23] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.921 ns" { int_div:inst6|clk_div[23] int_div:inst6|LessThan0~708 int_div:inst6|LessThan0~710 int_div:inst6|LessThan0~716 int_div:inst6|clk_div[5] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.921 ns" { int_div:inst6|clk_div[23] {} int_div:inst6|LessThan0~708 {} int_div:inst6|LessThan0~710 {} int_div:inst6|LessThan0~716 {} int_div:inst6|clk_div[5] {} } { 0.000ns 1.220ns 1.216ns 0.422ns 1.281ns } { 0.000ns 0.442ns 0.114ns 0.114ns 1.112ns } "" } } { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk int_div:inst6|clk_div[5] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} int_div:inst6|clk_div[5] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk int_div:inst6|clk_div[23] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} int_div:inst6|clk_div[23] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "segmain:inst1\|count\[6\] reset clk 8.643 ns register " "Info: tsu for register \"segmain:inst1\|count\[6\]\" (data pin = \"reset\", clock pin = \"clk\") is 8.643 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.515 ns + Longest pin register " "Info: + Longest pin to register delay is 11.515 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 PIN PIN_61 31 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_61; Fanout = 31; PIN Node = 'reset'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "G:/Q71/verilog/seg7led/seg7led.bdf" { { 112 -16 152 128 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.928 ns) + CELL(1.112 ns) 11.515 ns segmain:inst1\|count\[6\] 2 REG LC_X32_Y9_N9 2 " "Info: 2: + IC(8.928 ns) + CELL(1.112 ns) = 11.515 ns; Loc. = LC_X32_Y9_N9; Fanout = 2; REG Node = 'segmain:inst1\|count\[6\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.040 ns" { reset segmain:inst1|count[6] } "NODE_NAME" } } { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.587 ns ( 22.47 % ) " "Info: Total cell delay = 2.587 ns ( 22.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.928 ns ( 77.53 % ) " "Info: Total interconnect delay = 8.928 ns ( 77.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.515 ns" { reset segmain:inst1|count[6] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.515 ns" { reset {} reset~out0 {} segmain:inst1|count[6] {} } { 0.000ns 0.000ns 8.928ns } { 0.000ns 1.475ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.909 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 48 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 48; CLK Node = 'clk'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "G:/Q71/verilog/seg7led/seg7led.bdf" { { 64 -16 152 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns segmain:inst1\|count\[6\] 2 REG LC_X32_Y9_N9 2 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X32_Y9_N9; Fanout = 2; REG Node = 'segmain:inst1\|count\[6\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.440 ns" { clk segmain:inst1|count[6] } "NODE_NAME" } } { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk segmain:inst1|count[6] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk {} clk~out0 {} segmain:inst1|count[6] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.515 ns" { reset segmain:inst1|count[6] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.515 ns" { reset {} reset~out0 {} segmain:inst1|count[6] {} } { 0.000ns 0.000ns 8.928ns } { 0.000ns 1.475ns 1.112ns } "" } } { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.909 ns" { clk segmain:inst1|count[6] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.909 ns" { clk {} clk~out0 {} segmain:inst1|count[6] {} } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk 78leddata\[3\] lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[7\] 17.319 ns register " "Info: tco from clock \"clk\" to destination pin \"78leddata\[3\]\" through register \"lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[7\]\" is 17.319 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.326 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.326 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 48 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 48; CLK Node = 'clk'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "G:/Q71/verilog/seg7led/seg7led.bdf" { { 64 -16 152 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.935 ns) 3.178 ns int_div:inst6\|div_out 2 REG LC_X7_Y18_N2 17 " "Info: 2: + IC(0.774 ns) + CELL(0.935 ns) = 3.178 ns; Loc. = LC_X7_Y18_N2; Fanout = 17; REG Node = 'int_div:inst6\|div_out'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.709 ns" { clk int_div:inst6|div_out } "NODE_NAME" } } { "int_div.v" "" { Text "G:/Q71/verilog/seg7led/int_div.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.437 ns) + CELL(0.711 ns) 8.326 ns lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[7\] 3 REG LC_X32_Y7_N9 3 " "Info: 3: + IC(4.437 ns) + CELL(0.711 ns) = 8.326 ns; Loc. = LC_X32_Y7_N9; Fanout = 3; REG Node = 'lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[7\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.148 ns" { int_div:inst6|div_out lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] } "NODE_NAME" } } { "db/cntr_dth.tdf" "" { Text "G:/Q71/verilog/seg7led/db/cntr_dth.tdf" 163 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 37.41 % ) " "Info: Total cell delay = 3.115 ns ( 37.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.211 ns ( 62.59 % ) " "Info: Total interconnect delay = 5.211 ns ( 62.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.326 ns" { clk int_div:inst6|div_out lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.326 ns" { clk {} clk~out0 {} int_div:inst6|div_out {} lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] {} } { 0.000ns 0.000ns 0.774ns 4.437ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_dth.tdf" "" { Text "G:/Q71/verilog/seg7led/db/cntr_dth.tdf" 163 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.769 ns + Longest register pin " "Info: + Longest register to pin delay is 8.769 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[7\] 1 REG LC_X32_Y7_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X32_Y7_N9; Fanout = 3; REG Node = 'lpm_counter0:inst\|lpm_counter:lpm_counter_component\|cntr_dth:auto_generated\|safe_q\[7\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] } "NODE_NAME" } } { "db/cntr_dth.tdf" "" { Text "G:/Q71/verilog/seg7led/db/cntr_dth.tdf" 163 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.590 ns) 1.145 ns segmain:inst1\|Mux0~13 2 COMB LC_X32_Y7_N0 1 " "Info: 2: + IC(0.555 ns) + CELL(0.590 ns) = 1.145 ns; Loc. = LC_X32_Y7_N0; Fanout = 1; COMB Node = 'segmain:inst1\|Mux0~13'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.145 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] segmain:inst1|Mux0~13 } "NODE_NAME" } } { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.193 ns) + CELL(0.590 ns) 2.928 ns segmain:inst1\|Mux0~14 3 COMB LC_X32_Y6_N9 7 " "Info: 3: + IC(1.193 ns) + CELL(0.590 ns) = 2.928 ns; Loc. = LC_X32_Y6_N9; Fanout = 7; COMB Node = 'segmain:inst1\|Mux0~14'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.783 ns" { segmain:inst1|Mux0~13 segmain:inst1|Mux0~14 } "NODE_NAME" } } { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.325 ns) + CELL(0.292 ns) 4.545 ns segmain:inst1\|WideOr3~17 4 COMB LC_X33_Y7_N2 1 " "Info: 4: + IC(1.325 ns) + CELL(0.292 ns) = 4.545 ns; Loc. = LC_X33_Y7_N2; Fanout = 1; COMB Node = 'segmain:inst1\|WideOr3~17'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.617 ns" { segmain:inst1|Mux0~14 segmain:inst1|WideOr3~17 } "NODE_NAME" } } { "segmain.v" "" { Text "G:/Q71/verilog/seg7led/segmain.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.124 ns) 8.769 ns 78leddata\[3\] 5 PIN PIN_158 0 " "Info: 5: + IC(2.100 ns) + CELL(2.124 ns) = 8.769 ns; Loc. = PIN_158; Fanout = 0; PIN Node = '78leddata\[3\]'" {  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.224 ns" { segmain:inst1|WideOr3~17 78leddata[3] } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "G:/Q71/verilog/seg7led/seg7led.bdf" { { 176 632 808 192 "78leddata\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.596 ns ( 41.01 % ) " "Info: Total cell delay = 3.596 ns ( 41.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.173 ns ( 58.99 % ) " "Info: Total interconnect delay = 5.173 ns ( 58.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.769 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] segmain:inst1|Mux0~13 segmain:inst1|Mux0~14 segmain:inst1|WideOr3~17 78leddata[3] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.769 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] {} segmain:inst1|Mux0~13 {} segmain:inst1|Mux0~14 {} segmain:inst1|WideOr3~17 {} 78leddata[3] {} } { 0.000ns 0.555ns 1.193ns 1.325ns 2.100ns } { 0.000ns 0.590ns 0.590ns 0.292ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.326 ns" { clk int_div:inst6|div_out lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.326 ns" { clk {} clk~out0 {} int_div:inst6|div_out {} lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] {} } { 0.000ns 0.000ns 0.774ns 4.437ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.769 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] segmain:inst1|Mux0~13 segmain:inst1|Mux0~14 segmain:inst1|WideOr3~17 78leddata[3] } "NODE_NAME" } } { "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "g:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.769 ns" { lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_dth:auto_generated|safe_q[7] {} segmain:inst1|Mux0~13 {} segmain:inst1|Mux0~14 {} segmain:inst1|WideOr3~17 {} 78leddata[3] {} } { 0.000ns 0.555ns 1.193ns 1.325ns 2.100ns } { 0.000ns 0.590ns 0.590ns 0.292ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}