vga.tan.qmsg

Verilog 经典实例

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "reset register register VGAsignal:inst1\|MMD\[0\] VGAsignal:inst1\|MMD\[1\] 304.04 MHz Internal " "Info: Clock \"reset\" Internal fmax is restricted to 304.04 MHz between source register \"VGAsignal:inst1\|MMD\[0\]\" and destination register \"VGAsignal:inst1\|MMD\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.289 ns " "Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.799 ns + Longest register register " "Info: + Longest register to register delay is 1.799 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsignal:inst1\|MMD\[0\] 1 REG LC_X15_Y7_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y7_N0; Fanout = 5; REG Node = 'VGAsignal:inst1\|MMD\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { VGAsignal:inst1|MMD[0] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.804 ns) 1.799 ns VGAsignal:inst1\|MMD\[1\] 2 REG LC_X15_Y7_N9 5 " "Info: 2: + IC(0.995 ns) + CELL(0.804 ns) = 1.799 ns; Loc. = LC_X15_Y7_N9; Fanout = 5; REG Node = 'VGAsignal:inst1\|MMD\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "1.799 ns" { VGAsignal:inst1|MMD[0] VGAsignal:inst1|MMD[1] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.804 ns ( 44.69 % ) " "Info: Total cell delay = 0.804 ns ( 44.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.995 ns ( 55.31 % ) " "Info: Total interconnect delay = 0.995 ns ( 55.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "1.799 ns" { VGAsignal:inst1|MMD[0] VGAsignal:inst1|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.799 ns" { VGAsignal:inst1|MMD[0] VGAsignal:inst1|MMD[1] } { 0.000ns 0.995ns } { 0.000ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset destination 6.836 ns + Shortest register " "Info: + Shortest clock path from clock \"reset\" to destination register is 6.836 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 CLK PIN_93 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'reset'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { reset } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 168 -16 152 184 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.786 ns) + CELL(0.918 ns) 6.836 ns VGAsignal:inst1\|MMD\[1\] 2 REG LC_X15_Y7_N9 5 " "Info: 2: + IC(4.786 ns) + CELL(0.918 ns) = 6.836 ns; Loc. = LC_X15_Y7_N9; Fanout = 5; REG Node = 'VGAsignal:inst1\|MMD\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "5.704 ns" { reset VGAsignal:inst1|MMD[1] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 29.99 % ) " "Info: Total cell delay = 2.050 ns ( 29.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.786 ns ( 70.01 % ) " "Info: Total interconnect delay = 4.786 ns ( 70.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "6.836 ns" { reset VGAsignal:inst1|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.836 ns" { reset reset~combout VGAsignal:inst1|MMD[1] } { 0.000ns 0.000ns 4.786ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset source 6.836 ns - Longest register " "Info: - Longest clock path from clock \"reset\" to source register is 6.836 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 CLK PIN_93 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'reset'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { reset } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 168 -16 152 184 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.786 ns) + CELL(0.918 ns) 6.836 ns VGAsignal:inst1\|MMD\[0\] 2 REG LC_X15_Y7_N0 5 " "Info: 2: + IC(4.786 ns) + CELL(0.918 ns) = 6.836 ns; Loc. = LC_X15_Y7_N0; Fanout = 5; REG Node = 'VGAsignal:inst1\|MMD\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "5.704 ns" { reset VGAsignal:inst1|MMD[0] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 29.99 % ) " "Info: Total cell delay = 2.050 ns ( 29.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.786 ns ( 70.01 % ) " "Info: Total interconnect delay = 4.786 ns ( 70.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "6.836 ns" { reset VGAsignal:inst1|MMD[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.836 ns" { reset reset~combout VGAsignal:inst1|MMD[0] } { 0.000ns 0.000ns 4.786ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "6.836 ns" { reset VGAsignal:inst1|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.836 ns" { reset reset~combout VGAsignal:inst1|MMD[1] } { 0.000ns 0.000ns 4.786ns } { 0.000ns 1.132ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "6.836 ns" { reset VGAsignal:inst1|MMD[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.836 ns" { reset reset~combout VGAsignal:inst1|MMD[0] } { 0.000ns 0.000ns 4.786ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 37 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 37 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "1.799 ns" { VGAsignal:inst1|MMD[0] VGAsignal:inst1|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.799 ns" { VGAsignal:inst1|MMD[0] VGAsignal:inst1|MMD[1] } { 0.000ns 0.995ns } { 0.000ns 0.804ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "6.836 ns" { reset VGAsignal:inst1|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.836 ns" { reset reset~combout VGAsignal:inst1|MMD[1] } { 0.000ns 0.000ns 4.786ns } { 0.000ns 1.132ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "6.836 ns" { reset VGAsignal:inst1|MMD[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.836 ns" { reset reset~combout VGAsignal:inst1|MMD[0] } { 0.000ns 0.000ns 4.786ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { VGAsignal:inst1|MMD[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { VGAsignal:inst1|MMD[1] } {  } {  } } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 37 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk b VGAsignal:inst1\|LL\[4\] 24.529 ns register " "Info: tco from clock \"clk\" to destination pin \"b\" through register \"VGAsignal:inst1\|LL\[4\]\" is 24.529 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.368 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 13.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { clk } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns VGAsignal:inst1\|FS\[5\] 2 REG LC_X12_Y4_N0 7 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y4_N0; Fanout = 7; REG Node = 'VGAsignal:inst1\|FS\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "3.032 ns" { clk VGAsignal:inst1|FS[5] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.933 ns) + CELL(1.294 ns) 9.422 ns VGAsignal:inst1\|CC\[4\] 3 REG LC_X12_Y3_N1 15 " "Info: 3: + IC(3.933 ns) + CELL(1.294 ns) = 9.422 ns; Loc. = LC_X12_Y3_N1; Fanout = 15; REG Node = 'VGAsignal:inst1\|CC\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "5.227 ns" { VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 13.368 ns VGAsignal:inst1\|LL\[4\] 4 REG LC_X13_Y7_N5 8 " "Info: 4: + IC(3.028 ns) + CELL(0.918 ns) = 13.368 ns; Loc. = LC_X13_Y7_N5; Fanout = 8; REG Node = 'VGAsignal:inst1\|LL\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "3.946 ns" { VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[4] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 34.93 % ) " "Info: Total cell delay = 4.669 ns ( 34.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.699 ns ( 65.07 % ) " "Info: Total interconnect delay = 8.699 ns ( 65.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "13.368 ns" { clk VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.368 ns" { clk clk~combout VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[4] } { 0.000ns 0.000ns 1.738ns 3.933ns 3.028ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 73 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.785 ns + Longest register pin " "Info: + Longest register to pin delay is 10.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsignal:inst1\|LL\[4\] 1 REG LC_X13_Y7_N5 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y7_N5; Fanout = 8; REG Node = 'VGAsignal:inst1\|LL\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { VGAsignal:inst1|LL[4] } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.406 ns) + CELL(0.914 ns) 2.320 ns VGAsignal:inst1\|GRBY~816 2 COMB LC_X14_Y7_N8 2 " "Info: 2: + IC(1.406 ns) + CELL(0.914 ns) = 2.320 ns; Loc. = LC_X14_Y7_N8; Fanout = 2; COMB Node = 'VGAsignal:inst1\|GRBY~816'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "2.320 ns" { VGAsignal:inst1|LL[4] VGAsignal:inst1|GRBY~816 } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.753 ns) + CELL(0.200 ns) 3.273 ns VGAsignal:inst1\|GRBY\[1\]~821 3 COMB LC_X14_Y7_N0 1 " "Info: 3: + IC(0.753 ns) + CELL(0.200 ns) = 3.273 ns; Loc. = LC_X14_Y7_N0; Fanout = 1; COMB Node = 'VGAsignal:inst1\|GRBY\[1\]~821'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "0.953 ns" { VGAsignal:inst1|GRBY~816 VGAsignal:inst1|GRBY[1]~821 } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.805 ns) + CELL(0.511 ns) 4.589 ns VGAsignal:inst1\|GRBY\[1\]~824 4 COMB LC_X14_Y7_N4 1 " "Info: 4: + IC(0.805 ns) + CELL(0.511 ns) = 4.589 ns; Loc. = LC_X14_Y7_N4; Fanout = 1; COMB Node = 'VGAsignal:inst1\|GRBY\[1\]~824'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "1.316 ns" { VGAsignal:inst1|GRBY[1]~821 VGAsignal:inst1|GRBY[1]~824 } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.103 ns) + CELL(0.200 ns) 5.892 ns VGAsignal:inst1\|GRBP\[1\]~754 5 COMB LC_X15_Y7_N2 1 " "Info: 5: + IC(1.103 ns) + CELL(0.200 ns) = 5.892 ns; Loc. = LC_X15_Y7_N2; Fanout = 1; COMB Node = 'VGAsignal:inst1\|GRBP\[1\]~754'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "1.303 ns" { VGAsignal:inst1|GRBY[1]~824 VGAsignal:inst1|GRBP[1]~754 } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 6.397 ns VGAsignal:inst1\|B 6 COMB LC_X15_Y7_N3 1 " "Info: 6: + IC(0.305 ns) + CELL(0.200 ns) = 6.397 ns; Loc. = LC_X15_Y7_N3; Fanout = 1; COMB Node = 'VGAsignal:inst1\|B'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "0.505 ns" { VGAsignal:inst1|GRBP[1]~754 VGAsignal:inst1|B } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.066 ns) + CELL(2.322 ns) 10.785 ns b 7 PIN PIN_110 0 " "Info: 7: + IC(2.066 ns) + CELL(2.322 ns) = 10.785 ns; Loc. = PIN_110; Fanout = 0; PIN Node = 'b'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "4.388 ns" { VGAsignal:inst1|B b } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 192 472 648 208 "b" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.347 ns ( 40.31 % ) " "Info: Total cell delay = 4.347 ns ( 40.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.438 ns ( 59.69 % ) " "Info: Total interconnect delay = 6.438 ns ( 59.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "10.785 ns" { VGAsignal:inst1|LL[4] VGAsignal:inst1|GRBY~816 VGAsignal:inst1|GRBY[1]~821 VGAsignal:inst1|GRBY[1]~824 VGAsignal:inst1|GRBP[1]~754 VGAsignal:inst1|B b } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.785 ns" { VGAsignal:inst1|LL[4] VGAsignal:inst1|GRBY~816 VGAsignal:inst1|GRBY[1]~821 VGAsignal:inst1|GRBY[1]~824 VGAsignal:inst1|GRBP[1]~754 VGAsignal:inst1|B b } { 0.000ns 1.406ns 0.753ns 0.805ns 1.103ns 0.305ns 2.066ns } { 0.000ns 0.914ns 0.200ns 0.511ns 0.200ns 0.200ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "13.368 ns" { clk VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.368 ns" { clk clk~combout VGAsignal:inst1|FS[5] VGAsignal:inst1|CC[4] VGAsignal:inst1|LL[4] } { 0.000ns 0.000ns 1.738ns 3.933ns 3.028ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "10.785 ns" { VGAsignal:inst1|LL[4] VGAsignal:inst1|GRBY~816 VGAsignal:inst1|GRBY[1]~821 VGAsignal:inst1|GRBY[1]~824 VGAsignal:inst1|GRBP[1]~754 VGAsignal:inst1|B b } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.785 ns" { VGAsignal:inst1|LL[4] VGAsignal:inst1|GRBY~816 VGAsignal:inst1|GRBY[1]~821 VGAsignal:inst1|GRBY[1]~824 VGAsignal:inst1|GRBP[1]~754 VGAsignal:inst1|B b } { 0.000ns 1.406ns 0.753ns 0.805ns 1.103ns 0.305ns 2.066ns } { 0.000ns 0.914ns 0.200ns 0.511ns 0.200ns 0.200ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset g 10.058 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"g\" is 10.058 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 CLK PIN_93 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'reset'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "" { reset } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 168 -16 152 184 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.087 ns) + CELL(0.914 ns) 5.133 ns VGAsignal:inst1\|G 2 COMB LC_X13_Y7_N4 1 " "Info: 2: + IC(3.087 ns) + CELL(0.914 ns) = 5.133 ns; Loc. = LC_X13_Y7_N4; Fanout = 1; COMB Node = 'VGAsignal:inst1\|G'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "4.001 ns" { reset VGAsignal:inst1|G } "NODE_NAME" } "" } } { "VGAsignal.v" "" { Text "D:/Verilog_VGA/VGAsignal.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.603 ns) + CELL(2.322 ns) 10.058 ns g 3 PIN PIN_111 0 " "Info: 3: + IC(2.603 ns) + CELL(2.322 ns) = 10.058 ns; Loc. = PIN_111; Fanout = 0; PIN Node = 'g'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "4.925 ns" { VGAsignal:inst1|G g } "NODE_NAME" } "" } } { "VGA.bdf" "" { Schematic "D:/Verilog_VGA/VGA.bdf" { { 176 464 640 192 "g" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.368 ns ( 43.43 % ) " "Info: Total cell delay = 4.368 ns ( 43.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.690 ns ( 56.57 % ) " "Info: Total interconnect delay = 5.690 ns ( 56.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "VGA" "UNKNOWN" "V1" "D:/Verilog_VGA/db/VGA.quartus_db" { Floorplan "D:/Verilog_VGA/" "" "10.058 ns" { reset VGAsignal:inst1|G g } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.058 ns" { reset reset~combout VGAsignal:inst1|G g } { 0.000ns 0.000ns 3.087ns 2.603ns } { 0.000ns 1.132ns 0.914ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 19 23:32:22 2006 " "Info: Processing ended: Sun Nov 19 23:32:22 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}