vga.tan.rpt

Verilog 经典实例

; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Sun Nov 19 23:32:20 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off VGA -c VGA
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "reset" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "VGAsignal:inst1|FS[5]" as buffer
    Info: Detected ripple clock "VGAsignal:inst1|CC[4]" as buffer
Info: Clock "clk" has Internal fmax of 132.86 MHz between source register "VGAsignal:inst1|LL[2]" and destination register "VGAsignal:inst1|LL[7]" (period= 7.527 ns)
    Info: + Longest register to register delay is 6.818 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y7_N2; Fanout = 6; REG Node = 'VGAsignal:inst1|LL[2]'
        Info: 2: + IC(2.043 ns) + CELL(0.747 ns) = 2.790 ns; Loc. = LC_X12_Y7_N2; Fanout = 2; COMB Node = 'VGAsignal:inst1|add~381'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.913 ns; Loc. = LC_X12_Y7_N3; Fanout = 2; COMB Node = 'VGAsignal:inst1|add~351'
        Info: 4: + IC(0.000 ns) + CELL(0.261 ns) = 3.174 ns; Loc. = LC_X12_Y7_N4; Fanout = 4; COMB Node = 'VGAsignal:inst1|add~341'
        Info: 5: + IC(0.000 ns) + CELL(0.975 ns) = 4.149 ns; Loc. = LC_X12_Y7_N7; Fanout = 1; COMB Node = 'VGAsignal:inst1|add~344'
        Info: 6: + IC(1.865 ns) + CELL(0.804 ns) = 6.818 ns; Loc. = LC_X14_Y7_N5; Fanout = 10; REG Node = 'VGAsignal:inst1|LL[7]'
        Info: Total cell delay = 2.910 ns ( 42.68 % )
        Info: Total interconnect delay = 3.908 ns ( 57.32 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 13.368 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y4_N0; Fanout = 7; REG Node = 'VGAsignal:inst1|FS[5]'
            Info: 3: + IC(3.933 ns) + CELL(1.294 ns) = 9.422 ns; Loc. = LC_X12_Y3_N1; Fanout = 15; REG Node = 'VGAsignal:inst1|CC[4]'
            Info: 4: + IC(3.028 ns) + CELL(0.918 ns) = 13.368 ns; Loc. = LC_X14_Y7_N5; Fanout = 10; REG Node = 'VGAsignal:inst1|LL[7]'
            Info: Total cell delay = 4.669 ns ( 34.93 % )
            Info: Total interconnect delay = 8.699 ns ( 65.07 % )
        Info: - Longest clock path from clock "clk" to source register is 13.368 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y4_N0; Fanout = 7; REG Node = 'VGAsignal:inst1|FS[5]'
            Info: 3: + IC(3.933 ns) + CELL(1.294 ns) = 9.422 ns; Loc. = LC_X12_Y3_N1; Fanout = 15; REG Node = 'VGAsignal:inst1|CC[4]'
            Info: 4: + IC(3.028 ns) + CELL(0.918 ns) = 13.368 ns; Loc. = LC_X14_Y7_N2; Fanout = 6; REG Node = 'VGAsignal:inst1|LL[2]'
            Info: Total cell delay = 4.669 ns ( 34.93 % )
            Info: Total interconnect delay = 8.699 ns ( 65.07 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: Clock "reset" Internal fmax is restricted to 304.04 MHz between source register "VGAsignal:inst1|MMD[0]" and destination register "VGAsignal:inst1|MMD[1]"
    Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.799 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y7_N0; Fanout = 5; REG Node = 'VGAsignal:inst1|MMD[0]'
            Info: 2: + IC(0.995 ns) + CELL(0.804 ns) = 1.799 ns; Loc. = LC_X15_Y7_N9; Fanout = 5; REG Node = 'VGAsignal:inst1|MMD[1]'
            Info: Total cell delay = 0.804 ns ( 44.69 % )
            Info: Total interconnect delay = 0.995 ns ( 55.31 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "reset" to destination register is 6.836 ns
                Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'reset'
                Info: 2: + IC(4.786 ns) + CELL(0.918 ns) = 6.836 ns; Loc. = LC_X15_Y7_N9; Fanout = 5; REG Node = 'VGAsignal:inst1|MMD[1]'
                Info: Total cell delay = 2.050 ns ( 29.99 % )
                Info: Total interconnect delay = 4.786 ns ( 70.01 % )
            Info: - Longest clock path from clock "reset" to source register is 6.836 ns
                Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'reset'
                Info: 2: + IC(4.786 ns) + CELL(0.918 ns) = 6.836 ns; Loc. = LC_X15_Y7_N0; Fanout = 5; REG Node = 'VGAsignal:inst1|MMD[0]'
                Info: Total cell delay = 2.050 ns ( 29.99 % )
                Info: Total interconnect delay = 4.786 ns ( 70.01 % )
        Info: + Micro clock to output delay of source is 0.376 ns
        Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "b" through register "VGAsignal:inst1|LL[4]" is 24.529 ns
    Info: + Longest clock path from clock "clk" to source register is 13.368 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y4_N0; Fanout = 7; REG Node = 'VGAsignal:inst1|FS[5]'
        Info: 3: + IC(3.933 ns) + CELL(1.294 ns) = 9.422 ns; Loc. = LC_X12_Y3_N1; Fanout = 15; REG Node = 'VGAsignal:inst1|CC[4]'
        Info: 4: + IC(3.028 ns) + CELL(0.918 ns) = 13.368 ns; Loc. = LC_X13_Y7_N5; Fanout = 8; REG Node = 'VGAsignal:inst1|LL[4]'
        Info: Total cell delay = 4.669 ns ( 34.93 % )
        Info: Total interconnect delay = 8.699 ns ( 65.07 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 10.785 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y7_N5; Fanout = 8; REG Node = 'VGAsignal:inst1|LL[4]'
        Info: 2: + IC(1.406 ns) + CELL(0.914 ns) = 2.320 ns; Loc. = LC_X14_Y7_N8; Fanout = 2; COMB Node = 'VGAsignal:inst1|GRBY~816'
        Info: 3: + IC(0.753 ns) + CELL(0.200 ns) = 3.273 ns; Loc. = LC_X14_Y7_N0; Fanout = 1; COMB Node = 'VGAsignal:inst1|GRBY[1]~821'
        Info: 4: + IC(0.805 ns) + CELL(0.511 ns) = 4.589 ns; Loc. = LC_X14_Y7_N4; Fanout = 1; COMB Node = 'VGAsignal:inst1|GRBY[1]~824'
        Info: 5: + IC(1.103 ns) + CELL(0.200 ns) = 5.892 ns; Loc. = LC_X15_Y7_N2; Fanout = 1; COMB Node = 'VGAsignal:inst1|GRBP[1]~754'
        Info: 6: + IC(0.305 ns) + CELL(0.200 ns) = 6.397 ns; Loc. = LC_X15_Y7_N3; Fanout = 1; COMB Node = 'VGAsignal:inst1|B'
        Info: 7: + IC(2.066 ns) + CELL(2.322 ns) = 10.785 ns; Loc. = PIN_110; Fanout = 0; PIN Node = 'b'
        Info: Total cell delay = 4.347 ns ( 40.31 % )
        Info: Total interconnect delay = 6.438 ns ( 59.69 % )
Info: Longest tpd from source pin "reset" to destination pin "g" is 10.058 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 5; CLK Node = 'reset'
    Info: 2: + IC(3.087 ns) + CELL(0.914 ns) = 5.133 ns; Loc. = LC_X13_Y7_N4; Fanout = 1; COMB Node = 'VGAsignal:inst1|G'
    Info: 3: + IC(2.603 ns) + CELL(2.322 ns) = 10.058 ns; Loc. = PIN_111; Fanout = 0; PIN Node = 'g'
    Info: Total cell delay = 4.368 ns ( 43.43 % )
    Info: Total interconnect delay = 5.690 ns ( 56.57 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun Nov 19 23:32:22 2006
    Info: Elapsed time: 00:00:03