📄 vga.fit.rpt
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+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 7.22) ; Number of LABs (Total = 9) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 5 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 1.00) ; Number of LABs (Total = 9) ;
+------------------------------------+-----------------------------+
; 1 Clock ; 9 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 7.78) ; Number of LABs (Total = 9) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 2 ;
; 12 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 5.11) ; Number of LABs (Total = 9) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 3 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 0 ;
; 9 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 7.67) ; Number of LABs (Total = 9) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Sun Nov 19 23:32:03 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off VGA -c VGA
Info: Selected device EPM1270T144C5 for design "VGA"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Device EPM1270T144C5ES is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "VGAsignal:inst1|CC[4]" to use Global clock
Info: Destination "VGAsignal:inst1|GRBX[2]~516" may be non-global or may not use global clock
Info: Destination "VGAsignal:inst1|LessThan~988" may be non-global or may not use global clock
Info: Destination "VGAsignal:inst1|GRBX[3]~517" may be non-global or may not use global clock
Info: Destination "VGAsignal:inst1|GRBX[1]~518" may be non-global or may not use global clock
Info: Destination "VGAsignal:inst1|GRBX[1]~519" may be non-global or may not use global clock
Info: Destination "VGAsignal:inst1|add~374" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "VGAsignal:inst1|FS[5]" to use Global clock
Info: Destination "VGAsignal:inst1|add~399" may be non-global or may not use global clock
Info: Destination "VGAsignal:inst1|Equal~227" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "reset" to use Global clock
Info: Destination "VGAsignal:inst1|R" may be non-global or may not use global clock
Info: Destination "VGAsignal:inst1|G" may be non-global or may not use global clock
Info: Destination "VGAsignal:inst1|B" may be non-global or may not use global clock
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is register to pin delay of 11.263 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y7; Fanout = 10; REG Node = 'VGAsignal:inst1|LL[6]'
Info: 2: + IC(0.978 ns) + CELL(0.914 ns) = 1.892 ns; Loc. = LAB_X14_Y7; Fanout = 1; COMB Node = 'VGAsignal:inst1|GRBY[2]~814'
Info: 3: + IC(0.900 ns) + CELL(0.740 ns) = 3.532 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'VGAsignal:inst1|GRBY[2]~815'
Info: 4: + IC(0.269 ns) + CELL(0.914 ns) = 4.715 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'VGAsignal:inst1|GRBY[2]~817'
Info: 5: + IC(0.269 ns) + CELL(0.914 ns) = 5.898 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'VGAsignal:inst1|GRBP[2]~752'
Info: 6: + IC(0.443 ns) + CELL(0.740 ns) = 7.081 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'VGAsignal:inst1|R'
Info: 7: + IC(1.860 ns) + CELL(2.322 ns) = 11.263 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'r'
Info: Total cell delay = 6.544 ns ( 58.10 % )
Info: Total interconnect delay = 4.719 ns ( 41.90 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
Info: Fitter routing operations ending: elapsed time is 00:00:02
Info: The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Nov 19 23:32:13 2006
Info: Elapsed time: 00:00:11
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