serial_verilog.tan.rpt

Verilog 经典实例

; N/A                                     ; 140.71 MHz ( period = 7.107 ns )                    ; serial:inst|div_reg[10]      ; serial:inst|clkbaud8x   ; clk        ; clk      ; None                        ; None                      ; 6.398 ns                ;
; N/A                                     ; 141.06 MHz ( period = 7.089 ns )                    ; serial:inst|div_reg[10]      ; serial:inst|div_reg[1]  ; clk        ; clk      ; None                        ; None                      ; 6.380 ns                ;
; N/A                                     ; 141.06 MHz ( period = 7.089 ns )                    ; serial:inst|div_reg[10]      ; serial:inst|div_reg[0]  ; clk        ; clk      ; None                        ; None                      ; 6.380 ns                ;
; N/A                                     ; 141.06 MHz ( period = 7.089 ns )                    ; serial:inst|div_reg[10]      ; serial:inst|div_reg[7]  ; clk        ; clk      ; None                        ; None                      ; 6.380 ns                ;
; N/A                                     ; 141.06 MHz ( period = 7.089 ns )                    ; serial:inst|div_reg[10]      ; serial:inst|div_reg[6]  ; clk        ; clk      ; None                        ; None                      ; 6.380 ns                ;
; N/A                                     ; 141.06 MHz ( period = 7.089 ns )                    ; serial:inst|div_reg[10]      ; serial:inst|div_reg[3]  ; clk        ; clk      ; None                        ; None                      ; 6.380 ns                ;
; N/A                                     ; 141.06 MHz ( period = 7.089 ns )                    ; serial:inst|div_reg[10]      ; serial:inst|div_reg[2]  ; clk        ; clk      ; None                        ; None                      ; 6.380 ns                ;
; N/A                                     ; 141.06 MHz ( period = 7.089 ns )                    ; serial:inst|div_reg[10]      ; serial:inst|div_reg[4]  ; clk        ; clk      ; None                        ; None                      ; 6.380 ns                ;
; N/A                                     ; 141.06 MHz ( period = 7.089 ns )                    ; serial:inst|div_reg[10]      ; serial:inst|div_reg[5]  ; clk        ; clk      ; None                        ; None                      ; 6.380 ns                ;
; N/A                                     ; 141.56 MHz ( period = 7.064 ns )                    ; serial:inst|div8_tras_reg[1] ; serial:inst|txd_reg     ; clk        ; clk      ; None                        ; None                      ; 6.355 ns                ;
; N/A                                     ; 141.90 MHz ( period = 7.047 ns )                    ; serial:inst|div8_tras_reg[2] ; serial:inst|trasstart   ; clk        ; clk      ; None                        ; None                      ; 6.338 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                              ;                         ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+------------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------+
; tco                                                                            ;
+-------+--------------+------------+---------------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From                ; To      ; From Clock ;
+-------+--------------+------------+---------------------+---------+------------+
; N/A   ; None         ; 12.539 ns  ; serial:inst|txd_reg ; txd_usb ; clk        ;
+-------+--------------+------------+---------------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Sun Nov 19 22:43:03 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off serial_verilog -c serial_verilog
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "serial:inst|clkbaud8x" as buffer
Info: Clock "clk" has Internal fmax of 119.89 MHz between source register "serial:inst|div_reg[1]" and destination register "serial:inst|div_reg[12]" (period= 8.341 ns)
    Info: + Longest register to register delay is 7.632 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y4_N3; Fanout = 4; REG Node = 'serial:inst|div_reg[1]'
        Info: 2: + IC(1.269 ns) + CELL(0.914 ns) = 2.183 ns; Loc. = LC_X9_Y4_N9; Fanout = 1; COMB Node = 'serial:inst|LessThan~258'
        Info: 3: + IC(1.153 ns) + CELL(0.511 ns) = 3.847 ns; Loc. = LC_X10_Y4_N1; Fanout = 1; COMB Node = 'serial:inst|LessThan~259'
        Info: 4: + IC(0.728 ns) + CELL(0.200 ns) = 4.775 ns; Loc. = LC_X10_Y4_N0; Fanout = 17; COMB Node = 'serial:inst|LessThan~260'
        Info: 5: + IC(1.097 ns) + CELL(1.760 ns) = 7.632 ns; Loc. = LC_X11_Y4_N4; Fanout = 3; REG Node = 'serial:inst|div_reg[12]'
        Info: Total cell delay = 3.385 ns ( 44.35 % )
        Info: Total interconnect delay = 4.247 ns ( 55.65 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X11_Y4_N4; Fanout = 3; REG Node = 'serial:inst|div_reg[12]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
        Info: - Longest clock path from clock "clk" to source register is 3.819 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y4_N3; Fanout = 4; REG Node = 'serial:inst|div_reg[1]'
            Info: Total cell delay = 2.081 ns ( 54.49 % )
            Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "txd_usb" through register "serial:inst|txd_reg" is 12.539 ns
    Info: + Longest clock path from clock "clk" to source register is 9.035 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y4_N1; Fanout = 20; REG Node = 'serial:inst|clkbaud8x'
        Info: 3: + IC(3.922 ns) + CELL(0.918 ns) = 9.035 ns; Loc. = LC_X16_Y8_N2; Fanout = 3; REG Node = 'serial:inst|txd_reg'
        Info: Total cell delay = 3.375 ns ( 37.35 % )
        Info: Total interconnect delay = 5.660 ns ( 62.65 % )
    Info: + Micro clock to output dela