serial_verilog.tan.qmsg

Verilog 经典实例

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "serial:inst\|clkbaud8x " "Info: Detected ripple clock \"serial:inst\|clkbaud8x\" as buffer" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 33 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "serial:inst\|clkbaud8x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register serial:inst\|div_reg\[1\] register serial:inst\|div_reg\[12\] 119.89 MHz 8.341 ns Internal " "Info: Clock \"clk\" has Internal fmax of 119.89 MHz between source register \"serial:inst\|div_reg\[1\]\" and destination register \"serial:inst\|div_reg\[12\]\" (period= 8.341 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.632 ns + Longest register register " "Info: + Longest register to register delay is 7.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns serial:inst\|div_reg\[1\] 1 REG LC_X10_Y4_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y4_N3; Fanout = 4; REG Node = 'serial:inst\|div_reg\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "" { serial:inst|div_reg[1] } "NODE_NAME" } "" } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.269 ns) + CELL(0.914 ns) 2.183 ns serial:inst\|LessThan~258 2 COMB LC_X9_Y4_N9 1 " "Info: 2: + IC(1.269 ns) + CELL(0.914 ns) = 2.183 ns; Loc. = LC_X9_Y4_N9; Fanout = 1; COMB Node = 'serial:inst\|LessThan~258'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "2.183 ns" { serial:inst|div_reg[1] serial:inst|LessThan~258 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.153 ns) + CELL(0.511 ns) 3.847 ns serial:inst\|LessThan~259 3 COMB LC_X10_Y4_N1 1 " "Info: 3: + IC(1.153 ns) + CELL(0.511 ns) = 3.847 ns; Loc. = LC_X10_Y4_N1; Fanout = 1; COMB Node = 'serial:inst\|LessThan~259'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "1.664 ns" { serial:inst|LessThan~258 serial:inst|LessThan~259 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.728 ns) + CELL(0.200 ns) 4.775 ns serial:inst\|LessThan~260 4 COMB LC_X10_Y4_N0 17 " "Info: 4: + IC(0.728 ns) + CELL(0.200 ns) = 4.775 ns; Loc. = LC_X10_Y4_N0; Fanout = 17; COMB Node = 'serial:inst\|LessThan~260'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "0.928 ns" { serial:inst|LessThan~259 serial:inst|LessThan~260 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.097 ns) + CELL(1.760 ns) 7.632 ns serial:inst\|div_reg\[12\] 5 REG LC_X11_Y4_N4 3 " "Info: 5: + IC(1.097 ns) + CELL(1.760 ns) = 7.632 ns; Loc. = LC_X11_Y4_N4; Fanout = 3; REG Node = 'serial:inst\|div_reg\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "2.857 ns" { serial:inst|LessThan~260 serial:inst|div_reg[12] } "NODE_NAME" } "" } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.385 ns ( 44.35 % ) " "Info: Total cell delay = 3.385 ns ( 44.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.247 ns ( 55.65 % ) " "Info: Total interconnect delay = 4.247 ns ( 55.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "7.632 ns" { serial:inst|div_reg[1] serial:inst|LessThan~258 serial:inst|LessThan~259 serial:inst|LessThan~260 serial:inst|div_reg[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.632 ns" { serial:inst|div_reg[1] serial:inst|LessThan~258 serial:inst|LessThan~259 serial:inst|LessThan~260 serial:inst|div_reg[12] } { 0.000ns 1.269ns 1.153ns 0.728ns 1.097ns } { 0.000ns 0.914ns 0.511ns 0.200ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 17 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "" { clk } "NODE_NAME" } "" } } { "serial_verilog.bdf" "" { Schematic "D:/Test/serial_verilog/serial_verilog.bdf" { { 152 -8 160 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns serial:inst\|div_reg\[12\] 2 REG LC_X11_Y4_N4 3 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X11_Y4_N4; Fanout = 3; REG Node = 'serial:inst\|div_reg\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "2.656 ns" { clk serial:inst|div_reg[12] } "NODE_NAME" } "" } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "3.819 ns" { clk serial:inst|div_reg[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout serial:inst|div_reg[12] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 17 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "" { clk } "NODE_NAME" } "" } } { "serial_verilog.bdf" "" { Schematic "D:/Test/serial_verilog/serial_verilog.bdf" { { 152 -8 160 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns serial:inst\|div_reg\[1\] 2 REG LC_X10_Y4_N3 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y4_N3; Fanout = 4; REG Node = 'serial:inst\|div_reg\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "2.656 ns" { clk serial:inst|div_reg[1] } "NODE_NAME" } "" } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "3.819 ns" { clk serial:inst|div_reg[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout serial:inst|div_reg[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "3.819 ns" { clk serial:inst|div_reg[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout serial:inst|div_reg[12] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "3.819 ns" { clk serial:inst|div_reg[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout serial:inst|div_reg[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 52 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 52 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "7.632 ns" { serial:inst|div_reg[1] serial:inst|LessThan~258 serial:inst|LessThan~259 serial:inst|LessThan~260 serial:inst|div_reg[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.632 ns" { serial:inst|div_reg[1] serial:inst|LessThan~258 serial:inst|LessThan~259 serial:inst|LessThan~260 serial:inst|div_reg[12] } { 0.000ns 1.269ns 1.153ns 0.728ns 1.097ns } { 0.000ns 0.914ns 0.511ns 0.200ns 1.760ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "3.819 ns" { clk serial:inst|div_reg[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout serial:inst|div_reg[12] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "3.819 ns" { clk serial:inst|div_reg[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout serial:inst|div_reg[1] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk txd_usb serial:inst\|txd_reg 12.539 ns register " "Info: tco from clock \"clk\" to destination pin \"txd_usb\" through register \"serial:inst\|txd_reg\" is 12.539 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.035 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 9.035 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 17 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "" { clk } "NODE_NAME" } "" } } { "serial_verilog.bdf" "" { Schematic "D:/Test/serial_verilog/serial_verilog.bdf" { { 152 -8 160 168 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns serial:inst\|clkbaud8x 2 REG LC_X12_Y4_N1 20 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y4_N1; Fanout = 20; REG Node = 'serial:inst\|clkbaud8x'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "3.032 ns" { clk serial:inst|clkbaud8x } "NODE_NAME" } "" } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.922 ns) + CELL(0.918 ns) 9.035 ns serial:inst\|txd_reg 3 REG LC_X16_Y8_N2 3 " "Info: 3: + IC(3.922 ns) + CELL(0.918 ns) = 9.035 ns; Loc. = LC_X16_Y8_N2; Fanout = 3; REG Node = 'serial:inst\|txd_reg'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "4.840 ns" { serial:inst|clkbaud8x serial:inst|txd_reg } "NODE_NAME" } "" } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 37.35 % ) " "Info: Total cell delay = 3.375 ns ( 37.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.660 ns ( 62.65 % ) " "Info: Total interconnect delay = 5.660 ns ( 62.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "9.035 ns" { clk serial:inst|clkbaud8x serial:inst|txd_reg } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.035 ns" { clk clk~combout serial:inst|clkbaud8x serial:inst|txd_reg } { 0.000ns 0.000ns 1.738ns 3.922ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.128 ns + Longest register pin " "Info: + Longest register to pin delay is 3.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns serial:inst\|txd_reg 1 REG LC_X16_Y8_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y8_N2; Fanout = 3; REG Node = 'serial:inst\|txd_reg'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "" { serial:inst|txd_reg } "NODE_NAME" } "" } } { "serial.v" "" { Text "D:/Test/serial_verilog/serial.v" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.806 ns) + CELL(2.322 ns) 3.128 ns txd_usb 2 PIN PIN_105 0 " "Info: 2: + IC(0.806 ns) + CELL(2.322 ns) = 3.128 ns; Loc. = PIN_105; Fanout = 0; PIN Node = 'txd_usb'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "3.128 ns" { serial:inst|txd_reg txd_usb } "NODE_NAME" } "" } } { "serial_verilog.bdf" "" { Schematic "D:/Test/serial_verilog/serial_verilog.bdf" { { 152 376 552 168 "txd_usb" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 74.23 % ) " "Info: Total cell delay = 2.322 ns ( 74.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.806 ns ( 25.77 % ) " "Info: Total interconnect delay = 0.806 ns ( 25.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "3.128 ns" { serial:inst|txd_reg txd_usb } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.128 ns" { serial:inst|txd_reg txd_usb } { 0.000ns 0.806ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "9.035 ns" { clk serial:inst|clkbaud8x serial:inst|txd_reg } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.035 ns" { clk clk~combout serial:inst|clkbaud8x serial:inst|txd_reg } { 0.000ns 0.000ns 1.738ns 3.922ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "serial_verilog" "UNKNOWN" "V1" "D:/Test/serial_verilog/db/serial_verilog.quartus_db" { Floorplan "D:/Test/serial_verilog/" "" "3.128 ns" { serial:inst|txd_reg txd_usb } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.128 ns" { serial:inst|txd_reg txd_usb } { 0.000ns 0.806ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 19 22:43:05 2006 " "Info: Processing ended: Sun Nov 19 22:43:05 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}