📄 serial_verilog.fit.rpt
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; Direct links ; 33 / 3,938 ( < 1 % ) ;
; Global clocks ; 3 / 4 ( 75 % ) ;
; LAB clocks ; 12 / 72 ( 17 % ) ;
; LUT chains ; 11 / 1,143 ( < 1 % ) ;
; Local interconnects ; 83 / 3,938 ( 2 % ) ;
; R4s ; 29 / 2,832 ( 1 % ) ;
+----------------------------+----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 10) ;
+--------------------------------------------+------------------------------+
; 1 ; 2 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 2 ;
; 10 ; 6 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 10) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 9 ;
; 1 Clock ; 9 ;
; 1 Clock enable ; 1 ;
; 1 Sync. clear ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 10) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 2 ;
; 10 ; 6 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 4.90) ; Number of LABs (Total = 10) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 1 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 8.90) ; Number of LABs (Total = 10) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 2 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 18 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Sun Nov 19 22:42:50 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off serial_verilog -c serial_verilog
Info: Selected device EPM1270T144C5 for design "serial_verilog"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Device EPM1270T144C5ES is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Automatically promoted some destinations of signal "serial:inst|clkbaud8x" to use Global clock
Info: Destination "serial:inst|clkbaud8x" may be non-global or may not use global clock
Info: Automatically promoted signal "reset" to use Global clock
Info: Pin "reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Warning: Ignored locations or region assignments to the following nodes
Warning: Node "led[0]" is assigned to location or region, but does not exist in design
Warning: Node "led[1]" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:03
Info: Estimated most critical path is register to pin delay of 2.895 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X16_Y8; Fanout = 3; REG Node = 'serial:inst|txd_reg'
Info: 2: + IC(0.573 ns) + CELL(2.322 ns) = 2.895 ns; Loc. = PIN_105; Fanout = 0; PIN Node = 'txd_usb'
Info: Total cell delay = 2.322 ns ( 80.21 % )
Info: Total interconnect delay = 0.573 ns ( 19.79 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Quartus II Fitter was successful. 0 errors, 3 warnings
Info: Processing ended: Sun Nov 19 22:42:57 2006
Info: Elapsed time: 00:00:08
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