serial_verilog.map.eqn

Verilog 经典实例

--operation mode is arithmetic

B1_div_reg[10]_carry_eqn = B1L41;
B1_div_reg[10]_lut_out = B1_div_reg[10] $ (!B1_div_reg[10]_carry_eqn);
B1_div_reg[10] = DFFEAS(B1_div_reg[10]_lut_out, clk, reset, , , , , B1L6, );

--B1L43 is serial:inst|div_reg[10]~223
--operation mode is arithmetic

B1L43 = CARRY(B1_div_reg[10] & (!B1L41));


--B1_div_reg[11] is serial:inst|div_reg[11]
--operation mode is arithmetic

B1_div_reg[11]_carry_eqn = B1L43;
B1_div_reg[11]_lut_out = B1_div_reg[11] $ (B1_div_reg[11]_carry_eqn);
B1_div_reg[11] = DFFEAS(B1_div_reg[11]_lut_out, clk, reset, , , , , B1L6, );

--B1L45 is serial:inst|div_reg[11]~227
--operation mode is arithmetic

B1L45 = CARRY(!B1L43 # !B1_div_reg[11]);


--B1_div_reg[12] is serial:inst|div_reg[12]
--operation mode is arithmetic

B1_div_reg[12]_carry_eqn = B1L45;
B1_div_reg[12]_lut_out = B1_div_reg[12] $ (!B1_div_reg[12]_carry_eqn);
B1_div_reg[12] = DFFEAS(B1_div_reg[12]_lut_out, clk, reset, , , , , B1L6, );

--B1L47 is serial:inst|div_reg[12]~231
--operation mode is arithmetic

B1L47 = CARRY(B1_div_reg[12] & (!B1L45));


--B1L3 is serial:inst|LessThan~257
--operation mode is normal

B1L3 = !B1_div_reg[9] & !B1_div_reg[10] & !B1_div_reg[11] & !B1_div_reg[12];


--B1_div_reg[0] is serial:inst|div_reg[0]
--operation mode is arithmetic

B1_div_reg[0]_lut_out = !B1_div_reg[0];
B1_div_reg[0] = DFFEAS(B1_div_reg[0]_lut_out, clk, reset, , , , , B1L6, );

--B1L23 is serial:inst|div_reg[0]~235
--operation mode is arithmetic

B1L23 = CARRY(B1_div_reg[0]);


--B1_div_reg[1] is serial:inst|div_reg[1]
--operation mode is arithmetic

B1_div_reg[1]_carry_eqn = B1L23;
B1_div_reg[1]_lut_out = B1_div_reg[1] $ (B1_div_reg[1]_carry_eqn);
B1_div_reg[1] = DFFEAS(B1_div_reg[1]_lut_out, clk, reset, , , , , B1L6, );

--B1L25 is serial:inst|div_reg[1]~239
--operation mode is arithmetic

B1L25 = CARRY(!B1L23 # !B1_div_reg[1]);


--B1_div_reg[2] is serial:inst|div_reg[2]
--operation mode is arithmetic

B1_div_reg[2]_carry_eqn = B1L25;
B1_div_reg[2]_lut_out = B1_div_reg[2] $ (!B1_div_reg[2]_carry_eqn);
B1_div_reg[2] = DFFEAS(B1_div_reg[2]_lut_out, clk, reset, , , , , B1L6, );

--B1L27 is serial:inst|div_reg[2]~243
--operation mode is arithmetic

B1L27 = CARRY(B1_div_reg[2] & (!B1L25));


--B1_div_reg[3] is serial:inst|div_reg[3]
--operation mode is arithmetic

B1_div_reg[3]_carry_eqn = B1L27;
B1_div_reg[3]_lut_out = B1_div_reg[3] $ (B1_div_reg[3]_carry_eqn);
B1_div_reg[3] = DFFEAS(B1_div_reg[3]_lut_out, clk, reset, , , , , B1L6, );

--B1L29 is serial:inst|div_reg[3]~247
--operation mode is arithmetic

B1L29 = CARRY(!B1L27 # !B1_div_reg[3]);


--B1L4 is serial:inst|LessThan~258
--operation mode is normal

B1L4 = !B1_div_reg[2] & (!B1_div_reg[1] # !B1_div_reg[0]) # !B1_div_reg[3];


--B1_div_reg[4] is serial:inst|div_reg[4]
--operation mode is arithmetic

B1_div_reg[4]_carry_eqn = B1L29;
B1_div_reg[4]_lut_out = B1_div_reg[4] $ (!B1_div_reg[4]_carry_eqn);
B1_div_reg[4] = DFFEAS(B1_div_reg[4]_lut_out, clk, reset, , , , , B1L6, );

--B1L31 is serial:inst|div_reg[4]~251
--operation mode is arithmetic

B1L31 = CARRY(B1_div_reg[4] & (!B1L29));


--B1L5 is serial:inst|LessThan~259
--operation mode is normal

B1L5 = B1L2 & B1L3 & (B1L4 # !B1_div_reg[4]);


--B1_div_reg[13] is serial:inst|div_reg[13]
--operation mode is arithmetic

B1_div_reg[13]_carry_eqn = B1L47;
B1_div_reg[13]_lut_out = B1_div_reg[13] $ (B1_div_reg[13]_carry_eqn);
B1_div_reg[13] = DFFEAS(B1_div_reg[13]_lut_out, clk, reset, , , , , B1L6, );

--B1L49 is serial:inst|div_reg[13]~255
--operation mode is arithmetic

B1L49 = CARRY(!B1L47 # !B1_div_reg[13]);


--B1_div_reg[14] is serial:inst|div_reg[14]
--operation mode is arithmetic

B1_div_reg[14]_carry_eqn = B1L49;
B1_div_reg[14]_lut_out = B1_div_reg[14] $ (!B1_div_reg[14]_carry_eqn);
B1_div_reg[14] = DFFEAS(B1_div_reg[14]_lut_out, clk, reset, , , , , B1L6, );

--B1L51 is serial:inst|div_reg[14]~259
--operation mode is arithmetic

B1L51 = CARRY(B1_div_reg[14] & (!B1L49));


--B1_div_reg[15] is serial:inst|div_reg[15]
--operation mode is normal

B1_div_reg[15]_carry_eqn = B1L51;
B1_div_reg[15]_lut_out = B1_div_reg[15] $ (B1_div_reg[15]_carry_eqn);
B1_div_reg[15] = DFFEAS(B1_div_reg[15]_lut_out, clk, reset, , , , , B1L6, );


--B1L6 is serial:inst|LessThan~260
--operation mode is normal

B1L6 = B1_div_reg[13] # B1_div_reg[14] # B1_div_reg[15] # !B1L5;


--B1L12 is serial:inst|Select~2309
--operation mode is normal

B1L12 = B1_send_state[1] & (!B1_send_state[2]);


--B1_txd_buf[2] is serial:inst|txd_buf[2]
--operation mode is normal

B1_txd_buf[2]_lut_out = B1L74 & !B1_txd_buf[3] # !B1L74 & (!B1L13);
B1_txd_buf[2] = DFFEAS(B1_txd_buf[2]_lut_out, B1_clkbaud8x, reset, , B1L76, , , , );


--B1L79 is serial:inst|txd_buf[3]~2508
--operation mode is normal

B1L79 = B1_state_tras[3] & B1_state_tras[0] & !B1_state_tras[2] & !B1_state_tras[1];


--B1_txd_buf[3] is serial:inst|txd_buf[3]
--operation mode is normal

B1_txd_buf[3]_lut_out = B1L80 & (B1L91 # B1L81 & B1L82) # !B1L80 & B1L81 & B1L82;
B1_txd_buf[3] = DFFEAS(B1_txd_buf[3]_lut_out, B1_clkbaud8x, reset, , B1L84, , , , );


--B1L13 is serial:inst|Select~2311
--operation mode is normal

B1L13 = B1_send_state[0] & !B1_send_state[2] # !B1_send_state[1] # !B1_state_tras[1];


--B1L80 is serial:inst|txd_buf[3]~2509
--operation mode is normal

B1L80 = B1_state_tras[1] & !B1_state_tras[2] # !B1_state_tras[0] # !B1_state_tras[3];


--B1L81 is serial:inst|txd_buf[3]~2510
--operation mode is normal

B1L81 = B1_send_state[0] & (!B1_send_state[2]) # !B1_send_state[0] & !B1_send_state[1] & B1_send_state[2];


--B1L82 is serial:inst|txd_buf[3]~2511
--operation mode is normal

B1L82 = B1_state_tras[2] & B1_state_tras[1] & B1_state_tras[3] & B1_state_tras[0];


--B1_txd_buf[4] is serial:inst|txd_buf[4]
--operation mode is normal

B1_txd_buf[4]_lut_out = B1L86 & (B1_state_tras[1] # !B1L85 & B1_state_tras[2]) # !B1L86 & !B1L85;
B1_txd_buf[4] = DFFEAS(B1_txd_buf[4]_lut_out, B1_clkbaud8x, reset, , B1L84, , , , );


--B1L91 is serial:inst|txd_buf~2512
--operation mode is normal

B1L91 = B1L1 & (!B1_txd_buf[4]) # !B1L1 & B1_txd_buf[3];


--B1L83 is serial:inst|txd_buf[3]~2514
--operation mode is normal

B1L83 = B1_state_tras[2] & (!B1_state_tras[0] # !B1_state_tras[1]) # !B1_state_tras[2] & B1_state_tras[1];


--B1L84 is serial:inst|txd_buf[3]~2515
--operation mode is normal

B1L84 = B1_state_tras[3] & !B1L83 & (B1L1 # !B1_state_tras[0]) # !B1_state_tras[3] & (B1_state_tras[0] # B1L83);


--B1_txd_buf[5] is serial:inst|txd_buf[5]
--operation mode is normal

B1_txd_buf[5]_lut_out = B1L79 # B1L74 & (B1_txd_buf[6]) # !B1L74 & B1L98;
B1_txd_buf[5] = DFFEAS(B1_txd_buf[5]_lut_out, B1_clkbaud8x, reset, , B1L76, , , , );


--B1L85 is serial:inst|txd_buf[3]~2516
--operation mode is normal

B1L85 = B1L1 & (!B1_txd_buf[5]) # !B1L1 & !B1_txd_buf[4];


--B1L86 is serial:inst|txd_buf[3]~2517
--operation mode is normal

B1L86 = B1_state_tras[3] & B1_state_tras[0];


--B1L98 is serial:inst|txd_reg~716
--operation mode is normal

B1L98 = B1_send_state[2] & B1_send_state[1];


--B1_txd_buf[6] is serial:inst|txd_buf[6]
--operation mode is normal

B1_txd_buf[6]_lut_out = !B1L87 & (B1L1 # B1L82 # B1_txd_buf[6]);
B1_txd_buf[6] = DFFEAS(B1_txd_buf[6]_lut_out, B1_clkbaud8x, reset, , B1L84, , , , );


--B1L87 is serial:inst|txd_buf[3]~2519
--operation mode is normal

B1L87 = B1L86 & (B1_state_tras[2] & B1_state_tras[1] & !B1L98 # !B1_state_tras[2] & !B1_state_tras[1]);


--B1L99 is serial:inst|txd_reg~717
--operation mode is normal

B1L99 = B1L1 & (B1_state_tras[3] $ (B1_state_tras[2] # B1_state_tras[1]));


--B1L100 is serial:inst|txd_reg~718
--operation mode is normal

B1L100 = B1_div8_tras_reg[2] & B1_div8_tras_reg[1] & B1_div8_tras_reg[0] & B1L78;


--B1L76 is serial:inst|txd_buf[2]~2521
--operation mode is normal

B1L76 = B1_div8_tras_reg[2] & B1_div8_tras_reg[1] & B1_div8_tras_reg[0] & !B1L75;


--B1L14 is serial:inst|Select~2314
--operation mode is normal

B1L14 = !B1_state_tras[2] & !B1_state_tras[1] & (B1L95 # !B1_trasstart);


--rxd_usb is rxd_usb
--operation mode is input

rxd_usb = INPUT();


--reset is reset
--operation mode is input

reset = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--txd_usb is txd_usb
--operation mode is output

txd_usb = OUTPUT(!B1_txd_reg);