serial_verilog.map.eqn

Verilog 经典实例

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B1_txd_reg is serial:inst|txd_reg
--operation mode is normal

B1_txd_reg_lut_out = B1_txd_buf[0] & (B1L99 $ B1L97) # !B1_txd_buf[0] & !B1L94 & !B1L99 & B1L97;
B1_txd_reg = DFFEAS(B1_txd_reg_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1_txd_buf[0] is serial:inst|txd_buf[0]
--operation mode is normal

B1_txd_buf[0]_lut_out = B1L74 & (B1_txd_buf[1]) # !B1L74 & !B1L7;
B1_txd_buf[0] = DFFEAS(B1_txd_buf[0]_lut_out, B1_clkbaud8x, reset, , B1L76, , , , );


--B1_send_state[0] is serial:inst|send_state[0]
--operation mode is normal

B1_send_state[0]_lut_out = B1_send_state[0] $ (B1L58 & B1L59);
B1_send_state[0] = DFFEAS(B1_send_state[0]_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1_send_state[2] is serial:inst|send_state[2]
--operation mode is normal

B1_send_state[2]_lut_out = B1_send_state[2] $ (B1_send_state[0] & B1_send_state[1] & B1L57);
B1_send_state[2] = DFFEAS(B1_send_state[2]_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1_send_state[1] is serial:inst|send_state[1]
--operation mode is normal

B1_send_state[1]_lut_out = B1_send_state[1] $ (B1_send_state[0] & B1L58 & B1L59);
B1_send_state[1] = DFFEAS(B1_send_state[1]_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1L93 is serial:inst|txd_reg~710
--operation mode is normal

B1L93 = B1_send_state[0] & B1_send_state[2] & B1_send_state[1] & !B1_txd_reg;


--B1_state_tras[0] is serial:inst|state_tras[0]
--operation mode is normal

B1_state_tras[0]_lut_out = B1_state_tras[0] & !B1L1 # !B1_state_tras[0] & B1L1 & (B1_state_tras[3] # !B1L14);
B1_state_tras[0] = DFFEAS(B1_state_tras[0]_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1_div8_tras_reg[2] is serial:inst|div8_tras_reg[2]
--operation mode is normal

B1_div8_tras_reg[2]_lut_out = B1_div8_tras_reg[2] $ (B1_trasstart & B1_div8_tras_reg[1] & B1_div8_tras_reg[0]);
B1_div8_tras_reg[2] = DFFEAS(B1_div8_tras_reg[2]_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1_div8_tras_reg[1] is serial:inst|div8_tras_reg[1]
--operation mode is normal

B1_div8_tras_reg[1]_lut_out = B1_div8_tras_reg[1] $ (B1_trasstart & B1_div8_tras_reg[0]);
B1_div8_tras_reg[1] = DFFEAS(B1_div8_tras_reg[1]_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1_div8_tras_reg[0] is serial:inst|div8_tras_reg[0]
--operation mode is normal

B1_div8_tras_reg[0]_lut_out = B1_trasstart $ B1_div8_tras_reg[0];
B1_div8_tras_reg[0] = DFFEAS(B1_div8_tras_reg[0]_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1L15 is serial:inst|add~488
--operation mode is normal

B1L15 = B1_state_tras[0] & B1_div8_tras_reg[2] & B1_div8_tras_reg[1] & B1_div8_tras_reg[0];


--B1_state_tras[3] is serial:inst|state_tras[3]
--operation mode is normal

B1_state_tras[3]_lut_out = B1_state_tras[3] $ (B1_state_tras[2] & B1L1 & B1L8);
B1_state_tras[3] = DFFEAS(B1_state_tras[3]_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1L94 is serial:inst|txd_reg~711
--operation mode is normal

B1L94 = B1L93 # B1L15 & !B1_state_tras[3];


--B1L1 is serial:inst|Equal~48
--operation mode is normal

B1L1 = B1_div8_tras_reg[2] & B1_div8_tras_reg[1] & B1_div8_tras_reg[0];


--B1_state_tras[2] is serial:inst|state_tras[2]
--operation mode is normal

B1_state_tras[2]_lut_out = B1_state_tras[2] $ (B1_state_tras[1] & B1_state_tras[0] & B1L1);
B1_state_tras[2] = DFFEAS(B1_state_tras[2]_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1_state_tras[1] is serial:inst|state_tras[1]
--operation mode is normal

B1_state_tras[1]_lut_out = B1_state_tras[1] $ (B1L11 & (B1L1 # B1L9));
B1_state_tras[1] = DFFEAS(B1_state_tras[1]_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1L78 is serial:inst|txd_buf[3]~2505
--operation mode is normal

B1L78 = !B1_state_tras[2] & !B1_state_tras[1];


--B1L95 is serial:inst|txd_reg~712
--operation mode is normal

B1L95 = B1_send_state[0] & B1_send_state[2] & B1_send_state[1];


--B1_trasstart is serial:inst|trasstart
--operation mode is normal

B1_trasstart_lut_out = B1L66 & (B1L68 & (B1L69) # !B1L68 & B1_trasstart) # !B1L66 & (B1_trasstart # !B1L68 & !B1L69);
B1_trasstart = DFFEAS(B1_trasstart_lut_out, B1_clkbaud8x, reset, , , , , , );


--B1L96 is serial:inst|txd_reg~713
--operation mode is normal

B1L96 = B1_state_tras[0] # !B1_state_tras[3] & !B1L95 & B1_trasstart;


--B1L97 is serial:inst|txd_reg~714
--operation mode is normal

B1L97 = B1_txd_reg & (B1L96 & B1L100 # !B1L99) # !B1_txd_reg & B1L96 & (B1L100);


--B1_clkbaud8x is serial:inst|clkbaud8x
--operation mode is normal

B1_clkbaud8x_lut_out = B1_clkbaud8x $ B1L6;
B1_clkbaud8x = DFFEAS(B1_clkbaud8x_lut_out, clk, reset, , , , , , );


--B1L7 is serial:inst|Select~2300
--operation mode is normal

B1L7 = B1_send_state[2] & (!B1_send_state[1]) # !B1_send_state[2] & (B1_send_state[1] # !B1_send_state[0]) # !B1_state_tras[1];


--B1L74 is serial:inst|txd_buf[2]~2506
--operation mode is normal

B1L74 = !B1_state_tras[1] & (B1_state_tras[2] # !B1_state_tras[0]) # !B1_state_tras[3];


--B1_txd_buf[1] is serial:inst|txd_buf[1]
--operation mode is normal

B1_txd_buf[1]_lut_out = B1L79 # B1L74 & (B1_txd_buf[2]) # !B1L74 & !B1L12;
B1_txd_buf[1] = DFFEAS(B1_txd_buf[1]_lut_out, B1_clkbaud8x, reset, , B1L76, , , , );


--B1L75 is serial:inst|txd_buf[2]~2507
--operation mode is normal

B1L75 = B1_state_tras[0] & B1_state_tras[3] & (B1_state_tras[2] $ B1_state_tras[1]) # !B1_state_tras[0] & (B1_state_tras[3] $ (!B1_state_tras[2] & !B1_state_tras[1]));


--B1L58 is serial:inst|send_state[2]~167
--operation mode is normal

B1L58 = B1_state_tras[3] & B1_div8_tras_reg[2] & B1_div8_tras_reg[1] & B1_div8_tras_reg[0];


--B1L59 is serial:inst|send_state[2]~168
--operation mode is normal

B1L59 = B1_state_tras[2] & B1_state_tras[1] & B1_state_tras[0];


--B1L57 is serial:inst|send_state[2]~0
--operation mode is normal

B1L57 = B1_state_tras[3] & B1L1 & B1L59;


--B1L8 is serial:inst|Select~2303
--operation mode is normal

B1L8 = B1_state_tras[1] & B1_state_tras[0];


--B1L9 is serial:inst|Select~2305
--operation mode is normal

B1L9 = B1_state_tras[3] & (B1_state_tras[1] & (!B1_state_tras[0] # !B1_state_tras[2]) # !B1_state_tras[1] & B1_state_tras[2]);


--B1L10 is serial:inst|Select~2306
--operation mode is normal

B1L10 = B1_state_tras[0] & (B1_state_tras[1] $ !B1_state_tras[2] # !B1_state_tras[3]);


--B1L11 is serial:inst|Select~2307
--operation mode is normal

B1L11 = B1L9 & B1L15 & !B1L10 # !B1L9 & (B1L10);


--B1L66 is serial:inst|trasstart~469
--operation mode is normal

B1L66 = B1_state_tras[3] & (B1L1 # !B1_trasstart);


--B1L67 is serial:inst|trasstart~470
--operation mode is normal

B1L67 = B1_state_tras[1] # !B1_state_tras[3] & B1L95;


--B1L68 is serial:inst|trasstart~471
--operation mode is normal

B1L68 = B1_state_tras[2] # B1L58 & B1L67;


--B1L69 is serial:inst|trasstart~472
--operation mode is normal

B1L69 = B1_state_tras[2] & B1L58 & (!B1L67 # !B1_state_tras[0]) # !B1_state_tras[2] & (B1_state_tras[0] # B1L67);


--B1_div_reg[5] is serial:inst|div_reg[5]
--operation mode is arithmetic

B1_div_reg[5]_carry_eqn = B1L31;
B1_div_reg[5]_lut_out = B1_div_reg[5] $ (B1_div_reg[5]_carry_eqn);
B1_div_reg[5] = DFFEAS(B1_div_reg[5]_lut_out, clk, reset, , , , , B1L6, );

--B1L33 is serial:inst|div_reg[5]~203
--operation mode is arithmetic

B1L33 = CARRY(!B1L31 # !B1_div_reg[5]);


--B1_div_reg[6] is serial:inst|div_reg[6]
--operation mode is arithmetic

B1_div_reg[6]_carry_eqn = B1L33;
B1_div_reg[6]_lut_out = B1_div_reg[6] $ (!B1_div_reg[6]_carry_eqn);
B1_div_reg[6] = DFFEAS(B1_div_reg[6]_lut_out, clk, reset, , , , , B1L6, );

--B1L35 is serial:inst|div_reg[6]~207
--operation mode is arithmetic

B1L35 = CARRY(B1_div_reg[6] & (!B1L33));


--B1_div_reg[7] is serial:inst|div_reg[7]
--operation mode is arithmetic

B1_div_reg[7]_carry_eqn = B1L35;
B1_div_reg[7]_lut_out = B1_div_reg[7] $ (B1_div_reg[7]_carry_eqn);
B1_div_reg[7] = DFFEAS(B1_div_reg[7]_lut_out, clk, reset, , , , , B1L6, );

--B1L37 is serial:inst|div_reg[7]~211
--operation mode is arithmetic

B1L37 = CARRY(!B1L35 # !B1_div_reg[7]);


--B1_div_reg[8] is serial:inst|div_reg[8]
--operation mode is arithmetic

B1_div_reg[8]_carry_eqn = B1L37;
B1_div_reg[8]_lut_out = B1_div_reg[8] $ (!B1_div_reg[8]_carry_eqn);
B1_div_reg[8] = DFFEAS(B1_div_reg[8]_lut_out, clk, reset, , , , , B1L6, );

--B1L39 is serial:inst|div_reg[8]~215
--operation mode is arithmetic

B1L39 = CARRY(B1_div_reg[8] & (!B1L37));


--B1L2 is serial:inst|LessThan~256
--operation mode is normal

B1L2 = !B1_div_reg[5] & !B1_div_reg[6] & !B1_div_reg[7] & !B1_div_reg[8];


--B1_div_reg[9] is serial:inst|div_reg[9]
--operation mode is arithmetic

B1_div_reg[9]_carry_eqn = B1L39;
B1_div_reg[9]_lut_out = B1_div_reg[9] $ (B1_div_reg[9]_carry_eqn);
B1_div_reg[9] = DFFEAS(B1_div_reg[9]_lut_out, clk, reset, , , , , B1L6, );

--B1L41 is serial:inst|div_reg[9]~219
--operation mode is arithmetic

B1L41 = CARRY(!B1L39 # !B1_div_reg[9]);


--B1_div_reg[10] is serial:inst|div_reg[10]